2fsk_final.fnsim.qmsg

全数字fsk调制解调的实现 verilog源码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div1024.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div1024.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div1024-bdf_type " "Info: Found design unit 1: div1024-bdf_type" {  } { { "div1024.vhd" "" { Text "E:/quartus/program/2fsk_final/div1024.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0} { "Info" "ISGN_ENTITY_NAME" "1 div1024 " "Info: Found entity 1: div1024" {  } { { "div1024.vhd" "" { Text "E:/quartus/program/2fsk_final/div1024.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "2fsk_final " "Info: Elaborating entity \"2fsk_final\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0}
{ "Warning" "WGDFX_INCONSISTENT_DIMENSION" "" "Warning: Found inconsistent dimensions" {  } { { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -48 688 864 -32 "dout\[7..0\]" "" } { 456 1056 1232 472 "dout" "" } } } }  } 0 0 "Found inconsistent dimensions" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pj pj:inst7 " "Info: Elaborating entity \"pj\" for hierarchy \"pj:inst7\"" {  } { { "2fsk_final.bdf" "inst7" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 432 960 1056 528 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpf lpf:inst3 " "Info: Elaborating entity \"lpf\" for hierarchy \"lpf:inst3\"" {  } { { "2fsk_final.bdf" "inst3" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 416 720 816 512 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div64 div64:inst17 " "Info: Elaborating entity \"div64\" for hierarchy \"div64:inst17\"" {  } { { "2fsk_final.bdf" "inst17" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 568 136 232 664 "inst17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse pulse:inst8 " "Info: Elaborating entity \"pulse\" for hierarchy \"pulse:inst8\"" {  } { { "2fsk_final.bdf" "inst8" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 432 592 688 528 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wf wf:inst9 " "Info: Elaborating entity \"wf\" for hierarchy \"wf:inst9\"" {  } { { "2fsk_final.bdf" "inst9" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 448 440 536 544 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zx zx:inst10 " "Info: Elaborating entity \"zx\" for hierarchy \"zx:inst10\"" {  } { { "2fsk_final.bdf" "inst10" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 464 304 400 560 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mx_7821 mx_7821:inst6 " "Info: Elaborating entity \"mx_7821\" for hierarchy \"mx_7821:inst6\"" {  } { { "2fsk_final.bdf" "inst6" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 464 128 272 560 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux mux:inst5 " "Info: Elaborating entity \"mux\" for hierarchy \"mux:inst5\"" {  } { { "2fsk_final.bdf" "inst5" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -72 512 648 24 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "m mux.vhd(17) " "Warning (10492): VHDL Process Statement warning at mux.vhd(17): signal \"m\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "mux.vhd" "" { Text "E:/quartus/program/2fsk_final/mux.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m5 m5:inst4 " "Info: Elaborating entity \"m5\" for hierarchy \"m5:inst4\"" {  } { { "2fsk_final.bdf" "inst4" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 104 352 448 200 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div1024 div1024:inst15 " "Info: Elaborating entity \"div1024\" for hierarchy \"div1024:inst15\"" {  } { { "2fsk_final.bdf" "inst15" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 104 232 328 200 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div8 div8:inst " "Info: Elaborating entity \"div8\" for hierarchy \"div8:inst\"" {  } { { "2fsk_final.bdf" "inst" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -64 120 216 32 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f1_zb f1_zb:inst2 " "Info: Elaborating entity \"f1_zb\" for hierarchy \"f1_zb:inst2\"" {  } { { "2fsk_final.bdf" "inst2" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -104 352 464 -8 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom16_1.vhd 2 1 " "Warning: Using design file rom16_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom16_1-SYN " "Info: Found design unit 1: rom16_1-SYN" {  } { { "rom16_1.vhd" "" { Text "E:/quartus/program/2fsk_final/rom16_1.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0} { "Info" "ISGN_ENTITY_NAME" "1 rom16_1 " "Info: Found entity 1: rom16_1" {  } { { "rom16_1.vhd" "" { Text "E:/quartus/program/2fsk_final/rom16_1.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom16_1 f1_zb:inst2\|rom16_1:u1 " "Info: Elaborating entity \"rom16_1\" for hierarchy \"f1_zb:inst2\|rom16_1:u1\"" {  } { { "f1_zb.vhd" "u1" { Text "E:/quartus/program/2fsk_final/f1_zb.vhd" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "e:/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom f1_zb:inst2\|rom16_1:u1\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"f1_zb:inst2\|rom16_1:u1\|lpm_rom:lpm_rom_component\"" {  } { { "rom16_1.vhd" "lpm_rom_component" { Text "E:/quartus/program/2fsk_final/rom16_1.vhd" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0}