div8.map.summary

来自「全数字fsk调制解调的实现 verilog源码」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Fri Oct 24 15:09:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : div8
Top-level Entity Name : div8
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 3
    Dedicated logic registers : 3
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge