sin16.mif

全数字fsk调制解调的实现 verilog源码

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=16;

ADDRESS_RADIX=BIN;
DATA_RADIX=UNS;

CONTENT BEGIN
	00000  :   9;
	00001  :   37;
	00010  :   79;
	00011  :   128;
	00100  :   176;
	00101  :   218;
	00110  :   246;
	00111  :   255;
	01000  :   246;
	01001  :   218;
	01010  :   176;
	01011  :   128;
	01100  :   79;
	01101  :   37;
	01110  :   9;
	01111  :   0;
END;