pulse.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pulse is
port (clk,rin : in std_logic;
      rout :out std_logic
      ) ;
end pulse;


architecture pulse of pulse is
signal q: std_logic_vector (15 downto 0);
begin
process (clk)
begin
if clk'event and clk='1' then 
q(15 downto 1)<=q(14 downto 0);
q(0)<=rin;
    if q(15 downto 0)="0000000000000000" then 
    rout<='0';
    else rout<='1';
end if;
end if;
end process;
end pulse;