m5.vhd

全数字fsk调制解调的实现 verilog源码

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 
ENTITY m5 IS 
	port
	(
		clk :  IN  STD_LOGIC;
		mout :  OUT  STD_LOGIC
	);
END m5;

ARCHITECTURE bdf_type OF m5 IS 
constant mo :std_logic_vector(4 downto 0) :="10000";
signal c :std_logic_vector(4 downto 0);
signal d :std_logic_vector(4 downto 0);
begin
d(3 downto 0)<=c(4 downto 1);
d(4)<=c(2) xor c(0);
process(clk)
begin
IF clk'EVENT AND clk='1' THEN
 if (c="00000") then
c<=mo;
 
else
c(4 downto 0)<=d(4 downto 0);
  mout<=c(0);
end if; 
end if;
end process;
end bdf_type;