mx_7821.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

entity mx_7821 is
port (clk: in std_logic;
      din: in std_logic_vector (7 downto 0);
      dout: out std_logic_vector(7 downto 0);
      rd: out std_logic) ;
end mx_7821;

architecture mx_7821 of mx_7821 is 
signal count :integer range 0 to 15;
begin
process (clk)
begin 
if clk'event and clk='1' then 
   count<=count+1;
end if;
if clk'event and clk='1' then 
  if(count=0 or count=1 or count=2 or count=3 or count=4 or count=5 or count=6 or count=7) then
 rd<='1';
  else
rd<='0';
end if;
end if;
if clk'event and clk='1' then 
if count>=12 then
dout(7 downto 0)<=din(7 downto 0); 
end if ;
end if;
end process;
end mx_7821;