f2_zb.vhd.bak

全数字fsk调制解调的实现 verilog源码

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity f2_zb is
port (clk    :in  std_logic;  
      sin    :out std_logic_vector(7 downto 0));      
end f2_zb;

architecture behav of f2_zb is

signal count    :std_logic_vector(3 downto 0);


begin

process(clk)
begin
if clk'event and clk='1' then 
count<=count+1;        
end if ;                 
end process;

process(clk)
begin
if clk'event and clk='1' then 
case count is
when"0000"=> sin <="01001111";
when"0001"=> sin <="00100101";
when"0010"=> sin <="00001001";
when"0011"=> sin <="00000000";
when"0100"=> sin <="00001001";
when"0101"=> sin <="00100101";
when"0110"=> sin <="01001111";
when"0111"=> sin <="10000000";
when"1000"=> sin <="10110000";
when"1001"=> sin <="11011010";
when"1010"=> sin <="11110110";
when"1011"=> sin <="11111111";
when"1100"=> sin <="11110110";
when"1101"=> sin <="11011010";
when"1110"=> sin <="10110000";
when"1111"=> sin <="10000000";
when others=> null;
end case;
end if ;                 
end process;

end architecture behav;