transcript

开源软核处理器OpenRisc的SOPC设计

# Reading D:/Modeltech_6.0c/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0c Feb  2 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "E:/Work/Projects/sdb/Document/Manual/AR2000-OR1200/code/rtl/or1200-1.35/sim/rtl_sim/modelsim_sim/or1200.mpf" 
# Loading project or1200
# File does not exist: E:/Work/Projects/sdb/Design/Core/AR2000/OpenRISC/or1200-1.35/bench/verilog/or1200_top_bench.v
# 1 file could not be opened in editor
vsim work.or1200_top_bench
# vsim work.or1200_top_bench 
# Loading work.or1200_top_bench
# Loading work.or1200_top
# Loading work.or1200_wb_biu
# Loading work.or1200_immu_top
# Loading work.or1200_immu_tlb
# Loading work.or1200_spram_64x14
# Loading work.or1200_spram_64x22
# Loading work.or1200_ic_top
# Loading work.or1200_ic_fsm
# Loading work.or1200_ic_ram
# Loading work.or1200_spram_2048x32
# Loading work.or1200_ic_tag
# Loading work.or1200_spram_512x20
# Loading work.or1200_cpu
# Loading work.or1200_genpc
# Loading work.or1200_if
# Loading work.or1200_ctrl
# Loading work.or1200_rf
# Loading work.or1200_dpram_32x32
# Loading work.or1200_operandmuxes
# Loading work.or1200_alu
# Loading work.or1200_mult_mac
# Loading work.or1200_gmultp2_32x32
# Loading work.or1200_sprs
# Loading work.or1200_lsu
# Loading work.or1200_mem2reg
# Loading work.or1200_reg2mem
# Loading work.or1200_wbmux
# Loading work.or1200_freeze
# Loading work.or1200_except
# Loading work.or1200_cfgr
# Loading work.or1200_dmmu_top
# Loading work.or1200_dmmu_tlb
# Loading work.or1200_spram_64x24
# Loading work.or1200_dc_top
# Loading work.or1200_dc_fsm
# Loading work.or1200_dc_ram
# Loading work.or1200_spram_2048x8
# Loading work.or1200_dc_tag
# Loading work.or1200_sb
# Loading work.or1200_du
# Loading work.or1200_pic
# Loading work.or1200_tt
# Loading work.or1200_pm
view wave
# .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs
run -all
# Break at ../../../bench/verilog/or1200_top_bench.v line 188
do E:/Work/Projects/sdb/Document/Manual/AR2000-OR1200/code/rtl/or1200-1.35/sim/rtl_sim/modelsim_sim/wave.do
restart
run -all
# Break at ../../../bench/verilog/or1200_top_bench.v line 188