or1200.cr.mti

来自「开源软核处理器OpenRisc的SOPC设计」· MTI 代码 · 共 364 行 · 第 1/2 页

	or1200_sprs

} {} {}} ../../../rtl/verilog/or1200_spram_1024x8.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_1024x8.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_spram_1024x8

Top level modules:
	or1200_spram_1024x8

} {} {}} ../../../rtl/verilog/or1200_cfgr.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_cfgr.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_cfgr

Top level modules:
	or1200_cfgr

} {} {}} ../../../rtl/verilog/or1200_pic.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_pic.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_pic

Top level modules:
	or1200_pic

} {} {}} ../../../rtl/verilog/or1200_spram_2048x32.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_2048x32.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_spram_2048x32

Top level modules:
	or1200_spram_2048x32

} {} {}} ../../../rtl/verilog/or1200_rf.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_rf.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_rf

Top level modules:
	or1200_rf

} {} {}} ../../../rtl/verilog/or1200_dc_top.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_dc_top.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_dc_top

Top level modules:
	or1200_dc_top

} {} {}} ../../../rtl/verilog/or1200_ic_fsm.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_ic_fsm.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_ic_fsm

Top level modules:
	or1200_ic_fsm

} {} {}} ../../../rtl/verilog/or1200_spram_64x24.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_64x24.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_spram_64x24

Top level modules:
	or1200_spram_64x24

} {} {}} ../../../rtl/verilog/or1200_spram_256x21.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_256x21.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_spram_256x21

Top level modules:
	or1200_spram_256x21

} {} {}} ../../../rtl/verilog/or1200_rfram_generic.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_rfram_generic.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_rfram_generic

Top level modules:
	or1200_rfram_generic

} {} {}} ../../../rtl/verilog/or1200_pm.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_pm.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_pm

Top level modules:
	or1200_pm

} {} {}} ../../../rtl/verilog/or1200_reg2mem.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_reg2mem.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_reg2mem

Top level modules:
	or1200_reg2mem

} {} {}} ../../../rtl/verilog/or1200_spram_2048x8.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_2048x8.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_spram_2048x8

Top level modules:
	or1200_spram_2048x8

} {} {}} ../../../rtl/verilog/or1200_dc_tag.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_dc_tag.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_dc_tag

Top level modules:
	or1200_dc_tag

} {} {}} ../../../rtl/verilog/or1200_alu.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_alu.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_alu

Top level modules:
	or1200_alu

} {} {}} ../../../rtl/verilog/or1200_ic_ram.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_ic_ram.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_ic_ram

Top level modules:
	or1200_ic_ram

} {} {}} ../../../rtl/verilog/or1200_gmultp2_32x32.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_gmultp2_32x32.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_gmultp2_32x32

Top level modules:
	or1200_gmultp2_32x32

} {} {}} ../../../rtl/verilog/or1200_genpc.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_genpc.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_genpc

Top level modules:
	or1200_genpc

} {} {}} ../../../rtl/verilog/or1200_except.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_except.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_except

Top level modules:
	or1200_except

} {} {}} ../../../rtl/verilog/or1200_immu_top.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_immu_top.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_immu_top

Top level modules:
	or1200_immu_top

} {} {}} ../../../rtl/verilog/or1200_sb.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_sb.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_sb

Top level modules:
	or1200_sb

} {} {}} ../../../bench/verilog/or1200_top_bench.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../bench/verilog/or1200_top_bench.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_top_bench

Top level modules:
	or1200_top_bench

} {} {}} ../../../rtl/verilog/or1200_immu_tlb.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_immu_tlb.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_immu_tlb

Top level modules:
	or1200_immu_tlb

} {} {}} ../../../rtl/verilog/or1200_ic_top.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_ic_top.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_ic_top

Top level modules:
	or1200_ic_top

} {} {}} ../../../rtl/verilog/or1200_defines.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_defines.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005

} {} {}} ../../../rtl/verilog/or1200_if.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_if.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module or1200_if

Top level modules:
	or1200_if

} {} {}}