_primary.vhd

来自「开源软核处理器OpenRisc的SOPC设计」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity or1200_top_bench is
    generic(
        dw              : integer := 32;
        aw              : integer := 32;
        ppic_ints       : integer := 20
    );
end or1200_top_bench;