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o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_mult_macI]JUDOXLUA=YGn4BQc?X`f0V[F1=Y<U1jcO^H_odT24V;0dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_mult_mac.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 73OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_operandmuxesID7A8ODnnBXG2@^XKZ_ho40V_XO9lHE9YlN?PH]k@`nOe2dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_operandmuxes.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 78OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_picIMD2Zm3JQU:jJ?B87nY1VL2V_z0H?LLflICd8A8Lfa_Td1dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_pic.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 78OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_pmIk2T4>>0D4;IY3o5FEh?md1VdP2ng^A;j7@k[Bjhi;IS:3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_pm.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 72OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_reg2memIjk3c]MzPOA`=6o4Z98F_b0VTelm16l;^:PgclWjKNL<d3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_reg2mem.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 78OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_rfIC<AQSC`0h:C?dQYV>;9g82V^1P8Co<V6RIzjmEeG1`fC1dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_rf.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 93OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_rfram_genericI<RUS@PHOH^@ba?B8@Zj;e3VDC=2[omB>n>OHo1V5n?Dz2dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_rfram_generic.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 59OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_sbIJ<1P7f5@YGa_GgD3Fa<@A0VN4Og1M3_1mRLXTAfcJSDj0dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_sb.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 60OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_sb_fifoIQl04_7JM7B@^9eIbT[G2K0VlB2cGcX=8d^hH>fh9jjQ>1dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_sb_fifo.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 63OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_1024x32I8KaHYBjT:V4PE>ENacG?C0VNgj5RRCGdZSjhb0B_QAcg3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_1024x32.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 100OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_1024x8IQMQ:[SfSIoXIVCFJmAG8h3V4N0DH=G4FVY2eJSAQ`zdF0dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_1024x8.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 100OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_2048x32IeZ9F7G8Qc9V`H?oU=PQa31V>QX]e]FZzFOcU7SVY0SAQ3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_2048x32.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 103OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_2048x8I1W^T1]P@HB0;Y?@k`K=BK3Vo;kbeHFzV5dEoAKLZd3G_1dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_2048x8.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 100OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_256x21IMM^BaENMfiKNnf8oI[6kb1VSJHT_A[mCkFg_OOWGgcP32dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_256x21.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 106OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_512x20IfI0BmiL];cVX_W^mKHS2c0V2bAe08@8BJF1?;f0ABUC80dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_512x20.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 106OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_64x14IS@_0m0VWn864TO:kD]bh00VA10>_blj>>4H6WXWQmFJ81dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_64x14.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 100OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_64x22Ih@hDZ1BBaoZQ4ZSjnAFj71VCWIQdH8z`KkezJ22QAH[90dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_64x22.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 100OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_spram_64x24I97zP9kSkGUh]U>ca^NJbo2VCMYFPaI<N^_;4@znS@:RO3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_spram_64x24.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 103OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_sprsICDa=8JVOH:1bW18UUFAG93V9F9gR>Jmn_LWfm12zgJAA2dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_sprs.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 108OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_topI^CJ^7D2oLF:9G31IY<g9z3V4czFoEWRJB^JF^UbA93nk3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_top.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 114OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_top_benchIR:FYOZOgGYP1>KZV::L;01Vc`]3m<QcXJJdSKP[N7iBj2dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147105424F../../../bench/verilog/or1200_top_bench.vF../../../rtl/verilog/timescale.vL0 5OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_tpram_32x32I=:5^VfZU`CE;i4Z[3REIz2VLcz6>>ajKeUKJXbXZJESz3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_tpram_32x32.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 93OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_ttIzf`3SfN5JeO==22F62dBJ2V2H_h6mDJO5_gmH^SeXhD_3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_tt.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 87OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_wb_biuIfYA9Sl4]emdI0UlFZMBLR2VzZgeMOH`i;Z2KE6WL[M;g3dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_wb_biu.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 104OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000vor1200_wbmuxIkMMaS9Gnia>F01zn^SgBU2VaGHABF1j[FE>]oBdHRSY:2dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_simw1147703950F../../../rtl/verilog/or1200_wbmux.vF../../../rtl/verilog/timescale.vF../../../rtl/verilog/or1200_defines.vL0 75OE;L;6.0c;29r131o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work worktGenerateLoopIterationMax 100000⌨️ 快捷键说明
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