_info

开源软核处理器OpenRisc的SOPC设计

m255
13
cModel Technology
dD:\Modeltech_6.0c\examples
vor1200_alu
IO1MPVk^C>R?zmJhl0SiOI2
VlW@4a^64F=n;^>VJH`[QM2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_alu.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 108
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_cfgr
IZg2W]<i8S<13ZXK[C=n`J1
VWVajXcKaQlhKNAHf^IK0B0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_cfgr.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 78
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_cpu
IOgMX=nUd_W7Vn;=ba;R`_3
VEdNKoEB5nIk0FG6]LE<h@1
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_cpu.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 139
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_ctrl
INz7z`G81coXT;2GizV<1L2
VQoP`BRk<TI>_PGa3FJAD20
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_ctrl.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 111
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dc_fsm
IZh@=n^aIhL4Vd_IgN8hX40
VDo71MZ6lkmOc=SQF@oRha2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dc_fsm.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 107
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dc_ram
IdbaLgkaT_7F2PinnVW1c53
Vm4N1JOZ;YVS09daG_1Wga2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dc_ram.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 76
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dc_tag
IlNozjec0_8dg2`cI>QaYO3
VcCbHc<ba_CMSoEGiAUUd<1
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dc_tag.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 75
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dc_top
Ia4DHOcRo@01kRYYUczBH;0
V_D`Bbe^97iBKj_@aF_c9N2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dc_top.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 96
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dmmu_tlb
Ic4z?5;N]JVN>JEYc[HTAZ0
VcE2;eYL@J8GSnB1fIMVCY0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dmmu_tlb.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 79
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dmmu_top
I0DgB3Li;CbX4Lc7Z4Vh9B2
V[AQm40mzHA@XmhQ_A``QW3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dmmu_top.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 97
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_dpram_32x32
I?m0;DCC1JboiJa:^;kjlT0
VoZikRH_RLC05gGn^3ahhA0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_dpram_32x32.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 117
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_du
ICfUD9OcImDPl[i919TD==0
V:jHR?1ghQhoValeK1o=d62
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_du.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 106
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_except
IQ5`dz1;6JV3Hf=:WmSb<Z2
V>`bQc6iF]@?diV<_RQVoe2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_except.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 147
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_freeze
IQ9lJTKh9=E1Md]V>F5dbR3
VK>UJ@UY;aD[W?0MzeV[Xk0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_freeze.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 102
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_genpc
Ih8:hTDQJ@Ag?emj:6iZ^;1
V`EH4AGF30DPi;DSG4i<ad3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_genpc.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 96
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_gmultp2_32x32
I;ng[hB^o_O5kIoQYWoW7C3
VzFYd]dHB4JM4S8W50oG131
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_gmultp2_32x32.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 87
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_ic_fsm
IV>>NWZ<dm]?:nYhGMJ@`T3
VM<n9d2=WG^dY7gVLHfGPB3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_ic_fsm.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 109
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_ic_ram
If7ENCWf`?[XB:=OIF^6To1
V<GLEjl2WB3AA`o5BWT]:@3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_ic_ram.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 78
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_ic_tag
Ic?Q49P9fim38jRRzRdUid1
VIPDPhl@7oCLj0RN`>2LHW0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_ic_tag.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 78
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_ic_top
IOiU?QNR>oceJ_P@FY86O_1
VlVQH[0o?A35z7CLZJcgGF0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_ic_top.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 99
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_if
IkTGRe=IHdd]lZ@C2aU?<Z1
VMi@P:]Bb;CdWGonb?bgX_3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_if.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 84
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_immu_tlb
I7`So@i>A;df6[SPXYPAL53
VkFbVEO_UMO7LQNfn_4X>e3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_immu_tlb.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 85
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_immu_top
IDzd6Dj=lO2c3WNEAbo6]e2
V9^o=5:9kh5kBn:ColM2TN2
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_immu_top.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 112
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_lsu
IgA:HSbd?4>MAnWIkR@M2@2
VVJoo8i7`Fi4fgD]hVddbn0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_lsu.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 84
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vor1200_mem2reg
I^IUHZhA>HD3C=flXW0`H=1
Vg@i^J4]FXcJciHCb7UJ[;0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\or1200-1.35\sim\rtl_sim\modelsim_sim
w1147703950
F../../../rtl/verilog/or1200_mem2reg.v
F../../../rtl/verilog/timescale.v
F../../../rtl/verilog/or1200_defines.v
L0 87
OE;L;6.0c;29
r1
31