or1200.qsf

开源软核处理器OpenRisc的SOPC设计

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		or1200_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:01:46  MARCH 09, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP2"
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_alu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_amultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_cfgr.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_cpu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dc_fsm.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dc_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dc_tag.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dc_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_defines.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dmmu_tlb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dmmu_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_dpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_du.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_except.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_freeze.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_genpc.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_gmultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_ic_fsm.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_ic_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_ic_tag.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_ic_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_if.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_immu_tlb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_immu_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_lsu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_mem2reg.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_mult_mac.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_operandmuxes.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_pic.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_pm.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_reg2mem.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_rf.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_rfram_generic.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_sb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_sb_fifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_64x14.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_64x22.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_64x24.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_256x21.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_512x20.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_1024x8.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_1024x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_2048x8.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_spram_2048x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_sprs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_top.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_tpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_tt.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_wb_biu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_wbmux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/or1200_xcv_ram32x8d.v
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/timescale.v

# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY or1200_top

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C35F672C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF