transcript

开源软核处理器OpenRisc的SOPC设计

# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's3_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's3_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_adr_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_adr_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_adr_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_dat_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_adr_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_dat_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_dat_i'.
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO E:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC3\wb_conbusex\sim\rtl_sim\modelsim_sim\run.do PAUSED at line 8
# Compile of wb_conbusex_top_bench.v was successful.
# Compile of wb_conbusex_top_bench.v was successful.
vsim work.wb_conbusex_top_bench
# vsim work.wb_conbusex_top_bench 
# Loading work.wb_conbusex_top_bench
# Loading work.wb_conbusex_top
# Loading work.wb_conbus_arb
# Loading work.wb_mast
# Loading work.wb_slv
# ** Warning: (vsim-3017) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Too few port connections. Expected 266, found 242.
#         Region: /wb_conbusex_top_bench/conmax
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's15_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's14_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's13_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's12_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's11_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's10_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's9_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's8_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's7_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's6_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's5_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's4_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's3_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_cab_i'.
quit -sim
vsim work.wb_conbusex_top_bench
# vsim work.wb_conbusex_top_bench 
# Loading work.wb_conbusex_top_bench
# Loading work.wb_conbusex_top
# Loading work.wb_conbus_arb
# Loading work.wb_mast
# Loading work.wb_slv
# ** Warning: (vsim-3017) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Too few port connections. Expected 266, found 242.
#         Region: /wb_conbusex_top_bench/conmax
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's15_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's14_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's13_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's12_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's11_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's10_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's9_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's8_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's7_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's6_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's5_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's4_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's3_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's2_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's1_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 's0_cab_o'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm7_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm6_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm5_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm4_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm3_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm2_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm1_cab_i'.
# ** Warning: (vsim-3722) ../../../bench/verilog/wb_conbusex_top_bench.v(708): [TFMPC] - Missing connection for port 'm0_cab_i'.