wb_conbusex.cr.mti

开源软核处理器OpenRisc的SOPC设计

../../../rtl/verilog/timescale.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/timescale.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005

} {} {}} ../../../bench/verilog/wb_slv_model.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../bench/verilog/wb_slv_model.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module wb_slv

Top level modules:
	wb_slv

} {} {}} ../../../bench/verilog/wb_mast_model.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../bench/verilog/wb_mast_model.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module wb_mast

Top level modules:
	wb_mast

} {} {}} ../../../rtl/verilog/wb_conbusex_top.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/wb_conbusex_top.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module wb_conbusex_top

Top level modules:
	wb_conbusex_top

} {} {}} ../../../rtl/verilog/wb_conbus_arb.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/wb_conbus_arb.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module wb_conbus_arb

Top level modules:
	wb_conbus_arb

} {} {}}