_info

开源软核处理器OpenRisc的SOPC设计

m255
13
cModel Technology
dD:\Modeltech_6.0c\examples
vwb_conbus_arb
IUzgFm;YnCc3z[lLc`81QL3
V;;P=fjk4SU1FHR<L?hR]>0
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\wb_conbusex\sim\rtl_sim\modelsim_sim
w1112637916
F../../../rtl/verilog/wb_conbus_arb.v
F../../../rtl/verilog/timescale.v
L0 50
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vwb_conbusex_top
I7ZiImBmZbmPIS1QlQGVzS0
V3P>T`g]iPknzX@c8ce[TA3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\wb_conbusex\sim\rtl_sim\modelsim_sim
w1147274920
F../../../rtl/verilog/wb_conbusex_top.v
F../../../rtl/verilog/timescale.v
L0 60
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vwb_conbusex_top_bench
IcA[[UkW@9h7V^nh1^VUV71
Vo@z0^<ElYLgLS?k>Wbm@m1
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\wb_conbusex\sim\rtl_sim\modelsim_sim
w1147715458
F../../../bench/verilog/wb_conbusex_top_bench.v
F../../../rtl/verilog/timescale.v
L0 66
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vwb_mast
I2nQR64FMhma^eA>@kbKDn2
V:9K@3ZghWRlU7mCJE<DIT1
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\wb_conbusex\sim\rtl_sim\modelsim_sim
w1147272291
F../../../bench/verilog/wb_mast_model.v
F../../../rtl/verilog/timescale.v
L0 62
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000
vwb_slv
I0kk`RGVgT6h@X_6RN?1VH0
VfCU;?:h4EzEiSA431JHXE3
dE:\Work\Projects\sdb\Design\Core\AR2000\OpenRISC\wb_conbusex\sim\rtl_sim\modelsim_sim
w1147104844
F../../../bench/verilog/wb_slv_model.v
F../../../rtl/verilog/timescale.v
L0 71
OE;L;6.0c;29
r1
31
o+incdir+../../../rtl/verilog +incdir+../../../bench/verilog -work work
tGenerateLoopIterationMax 100000