ad_test.map.rpt

多功能卡的源代码

Analysis & Synthesis report for ad_test
Mon Mar 23 21:53:05 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |CPCI_exp|_422_to_fifo4:inst22|_422_receiver_2:inst|state
  9. State Machine - |CPCI_exp|_422_to_fifo3:inst21|_422_receiver_2:inst|state
 10. State Machine - |CPCI_exp|_422_to_fifo2:inst20|_422_receiver_2:inst|state
 11. State Machine - |CPCI_exp|_232_to_fifo:inst5|lt_uart_r5:inst6|add
 12. State Machine - |CPCI_exp|dma:inst6|currentstate
 13. State Machine - |CPCI_exp|_422_to_fifo1:inst8|_422_receiver_2:inst|state
 14. State Machine - |CPCI_exp|core1:inst23|current_state
 15. State Machine - |CPCI_exp|core1:inst23|operate_state
 16. Registers Removed During Synthesis
 17. General Register Statistics
 18. Inverted Register Statistics
 19. Multiplexer Restructuring Statistics (Restructuring Performed)
 20. Source assignments for _422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
 21. Source assignments for _232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo|altsyncram_boa1:FIFOram
 22. Source assignments for _422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
 23. Source assignments for _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
 24. Source assignments for _422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
 25. Source assignments for _back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo|altsyncram_71b1:FIFOram
 26. Source assignments for ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|dpram_cg01:FIFOram|altsyncram_onj1:altsyncram1
 27. Source assignments for adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|dpram_bg01:FIFOram|altsyncram_mnj1:altsyncram1
 28. Parameter Settings for User Entity Instance: core1:inst23
 29. Parameter Settings for User Entity Instance: _422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component
 30. Parameter Settings for User Entity Instance: dma:inst6
 31. Parameter Settings for User Entity Instance: altpll0:inst|altpll:altpll_component
 32. Parameter Settings for User Entity Instance: _232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component
 33. Parameter Settings for User Entity Instance: _232_to_fifo:inst5|clk_txd:inst1
 34. Parameter Settings for User Entity Instance: _422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component
 35. Parameter Settings for User Entity Instance: _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component
 36. Parameter Settings for User Entity Instance: _422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component
 37. Parameter Settings for User Entity Instance: _back_fifo:inst2|scfifo:scfifo_component
 38. Parameter Settings for User Entity Instance: ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component
 39. Parameter Settings for User Entity Instance: adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component
 40. scfifo Parameter Settings by Entity Instance
 41. Analysis & Synthesis Messages
 42. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;