clk_tran.v

来自「多功能卡的源代码」· Verilog 代码 · 共 11 行

module clk_tran(clkin,reset,clkout);
input clkin,reset;
output clkout;
reg [3:0]counter;
assign clkout=counter[0];
always @(posedge clkin or negedge reset)
begin
	if(!reset)	counter<=4'b0;
	else	counter<=counter+4'd1;
end 
endmodule