ds_ad_subctrl.v

多功能卡的源代码

module DS_ad_subctrl (	reset,S_CLK,sample_start,ad_read,ad_eoc,ad_cs,ad_conv,max_sel,
					ad_sel1,ad_sel2,ad_sel3,ad_sel4,busy,ram_addr,fifo_data,ram_ce1,ram_ce2,ram_we,ram_oe,
					ad_data,state,fifo_write,zijian_ctrl);
					
	input reset, S_CLK, sample_start, ad_eoc,busy;
	input [11:0]ad_data;
	
	output[3:0] max_sel,state;
	output ad_read, ad_sel1,ad_sel2, ad_sel3, ad_sel4, ad_conv,ad_cs;
	output [20:0]ram_addr;
	output [15:0]fifo_data;
	output ram_ce1,ram_ce2,ram_we,ram_oe,fifo_write;
	output [9:0] zijian_ctrl;
	
	reg [15:0]data;
	reg [20:0]addr;
	reg ad_cs;
	reg ad_read;
	reg[2:0] max_sel;
	reg ad_conv,ram_write;
	reg[3:0] state;
	reg fifo_write;
	reg [9:0] zijian_ctrl;
	reg [7:0] ds_testData;
	reg [15:0] fifo_data;
	//reg [15:0] data_buf;
	reg busy_flag;
	reg SCLK;
	//assign ad_cs=(reset)?1'b0:1'b1;
	assign ad_sel1=1'b1;
	assign ad_sel2=1'b1;//one chosed at one time of the two channels 
	assign ad_sel3=1'b1;
	assign ad_sel4=1'b1;
	assign ram_ce1=(!sample_start)?1'b0:1'b0;
	assign ram_ce2=(!sample_start)?1'b1:1'b0;
	assign ram_we=(!sample_start)?ram_write:1'b0;
	assign ram_oe=(!sample_start)?1'b0:1'b0;
	//assign fifo_data=(!sample_start)?data:16'h0;
	assign ram_addr=(!sample_start)?addr:21'b0;
	
	always @(posedge S_CLK or negedge reset)begin
		if(!reset) begin
			state <= 4'b0000;
			//max_sel <= 3'b000;
			//ad_sel1 <= 1'b1;
			ad_conv <= 1'b1;
			ad_read <= 1'b1;
			ram_write <= 1'b1;
			fifo_write <= 1'b0;
			addr<=21'b0;
			data<=16'b0;
			zijian_ctrl<=10'b0;
			ds_testData<=8'b0000_1000;
			busy_flag <= 1'b0;
			//data_buf <= 16'b0;
		end
		else begin
			if (sample_start) begin
			//zijian_ctrl<=10'b01_0101_0101;
				case(state)
					4'b0000: begin			
						//ad_sel1 <= 1'b1;
						ad_conv <= 1'b0;
						state <= 4'b0001;
						end
					4'b0001: begin
						state <= 4'b0011;
						end
					4'b0011: begin
						ad_conv <= 1'b1;
						state <= 4'b0010;
						end
					4'b0010: begin
						if(busy == 1) begin
							state <= 4'b0010;
							busy_flag <= 1'b1;
							end
						else if(busy == 0 && busy_flag == 1) begin
							ad_read <=1'b0;
							ad_cs <= 1'b0;
							fifo_write <= 1'b0;
							busy_flag <= 1'b0;
							state <=4'b0100;
							end
						else begin
							state <=4'b0000;
							ad_conv <= 1'b1;
							end	
						end
					4'b0100: begin
						fifo_data <= {2'b11,2'b00,ad_data[11:0]};//read the first data
						state <=4'b0101;	
						ad_read <=1'b1;
						ad_cs <= 1'b1;
						end
					4'b0101: begin
						ad_read <=1'b0;
						ad_cs <= 1'b0;
						//fifo_data <= 16'h0000;
						fifo_write <= 1'b1;
						state <=3'b0110;	
						end
					4'b0110: begin
						fifo_write <= 1'b0;
						fifo_data <= {2'b11,2'b01,ad_data[11:0]};//read the second data
						state <=4'b0111;	
						ad_read <=1'b1;
						ad_cs <= 1'b1;
						end
					4'b0111: begin
						ad_read <=1'b0;
						ad_cs <= 1'b0;
						//fifo_data <= 16'h0000;
						fifo_write <= 1'b1;
						state <=4'b1000;	
						end	
					4'b1000: begin
						fifo_write <= 1'b0;
						fifo_data <= {2'b11,2'b10,ad_data[11:0]};//read the third data
						state <=4'b1001;
						ad_read <=1'b1;
						ad_cs <= 1'b1;
						end
					4'b1001: begin
						ad_read <=1'b0;
						ad_cs <= 1'b0;
						//fifo_data <= 16'h0000;
						fifo_write <= 1'b1;
						state <=4'b1010;
						end
					4'b1010: begin
						fifo_write <= 1'b0;
						fifo_data <= {2'b11,2'b11,ad_data[11:0]};//read the third data
						state <=4'b1011;
						ad_read <=1'b1;
						ad_cs <= 1'b1;
				   	    end
				   	4'b1011: begin
						ad_read <=1'b1;
						ad_cs <= 1'b1;
						//fifo_data <= 16'h0000;
						fifo_write <= 1'b1;
						data <= 16'h0;
						state <=4'b1100;
						end
					4'b1100: begin
						state <=4'b0000;
						//fifo_data <= 16'h0000;
						fifo_write <= 1'b0;
						end
					default: begin
						state <=4'b0000;
						end
				endcase
				end
			else begin
				zijian_ctrl<=10'b11_1111_1111;
				ram_write<=1'b1;
				fifo_write <= 1'b0;
				data<=16'hzzzz;
				fifo_data <=16'hzzzz;
				end		
			end
		end
endmodule