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					RD_FIFO_ONE <= 1'b1;
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER[19:0];//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 32'd1;//计数器+1
					TOTAL_NUM_received <= TOTAL_NUM_received + 32'd1;
					bag_counter <= bag_counter+9'd1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd3;
				end
				else begin
					bag_counter <= 9'd0;
					fifo_sel[1]<=1'b1;
					operate_state <= 5'd20;
					//operate_state <= 5'd4;//进入第二通道
				end
			end
			/*5'd2:begin
				operate_state <= 5'd3;
				RD_FIFO_ONE <= 1'b0;
			end*/
			5'd3:begin	
				RAM_WE_ <= 1'b1;
				RD_FIFO_ONE <= 1'b0;
				operate_state <= 5'd1;		
			end
			//==================================================================================//
			/*
			5'd4:begin
				if(RHF_TWO_ == 1)begin             
					operate_state <= 5'd5;
					fifo_sel[2]<=1'b0;
				end
				else begin
					operate_state <= 5'd8;//第三通道
				end
			end
			*/
			5'd5:begin
			if(!bag_counter[8])begin
					RD_FIFO_TWO <= 1'b1;
					RAM_WE_ <= 1'b0;
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER[19:0];//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 32'd1;//计数器+1
					TOTAL_NUM_received <= TOTAL_NUM_received + 32'd1;
					bag_counter <= bag_counter+9'd1;
					operate_state <= 5'd7;  
				end
			else begin
					bag_counter <= 9'd0;
					fifo_sel[2]<=1'b1;
					operate_state <= 5'd20;
					//operate_state <= 5'd8;//第三通道
				end
				
			end
			/*5'd6:begin
				RD_FIFO_TWO <= 1'b0;
				operate_state <= 5'd7;
				end*/
			5'd7:begin
				RAM_WE_ <= 1'b1;
				RD_FIFO_TWO <= 1'b0;
				operate_state <= 5'd5;
			end
			//==================================================================================//
			/*
			5'd8:begin
				if(RHF_THREE_ == 1)begin
					operate_state <= 5'd9;
					fifo_sel[3]<=1'b0;
				end
				else begin
					operate_state <= 5'd12;//进入第四通道
				end
			end*/
			5'd9:begin
				if(!bag_counter[8])begin
					RD_FIFO_THREE <= 1'b1;
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER[19:0];//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 32'd1;//计数器+1
					TOTAL_NUM_received <= TOTAL_NUM_received + 32'd1;
					RAM_WE_ <= 1'b0;
					bag_counter <= bag_counter+9'd1;
					operate_state <= 5'd11;
				end
				else begin
					fifo_sel[3]<=1'b1;
					bag_counter <= 9'd0;
					operate_state <= 5'd20;
					//operate_state <= 5'd12;//进入第四通道
				end
			end
			/*5'd10:begin				
				operate_state <= 5'd11;
				RD_FIFO_THREE <= 1'b0;
				end*/
			5'd11:begin
				RAM_WE_ <= 1'b1;
				RD_FIFO_THREE <= 1'b0;
				operate_state <= 5'd9;
			end
			//==================================================================================//
			/*
			5'd12:begin
				if(RHF_FORE_ == 1)begin     
					operate_state <= 5'd13; 
					fifo_sel[4]<=1'b0;
				end
				else begin
					operate_state <= 5'd20;//结束
				end
			end*/
			5'd13:begin
				if(!bag_counter[8])begin
					RD_FIFO_FORE <= 1'b1;
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER[19:0];//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 32'd1;//计数器+1
					TOTAL_NUM_received <= TOTAL_NUM_received + 32'd1;
					RAM_WE_ <= 1'b0;
					bag_counter <= bag_counter+9'd1;
					operate_state <= 5'd15; 
				end
				else begin
					fifo_sel[4]<=1'b1;
					bag_counter <= 9'd0;
					operate_state <= 5'd20;//结束
				end
			end
			/*5'd14:begin
				operate_state <= 5'd15;	
				RD_FIFO_FORE <= 1'b0;
				end*/
			5'd15:begin
				RAM_WE_ <= 1'b1;
				RD_FIFO_FORE <= 1'b0;
				operate_state <= 5'd13; 
			end
			//==================================================================================//
			/*
			5'd16:begin
				if(RHF_232_ == 1)begin
					operate_state <= 5'd17;
					fifo_sel[0]<=1'b0;
				end
				else begin
					operate_state <= 5'd20;
				end
			end
			5'd17:begin
				if(!bag_counter[8])begin  
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER;
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;
					TOTAL_NUM_received <= TOTAL_NUM_received + 34'd1;
					RAM_WE_ <= 1'b0;
					RD_FIFO_232 <= 1'b1;
					bag_counter <= bag_counter+9'd1;
					operate_state <= 5'd18;
				end
				else begin
					fifo_sel[0]<=1'b1;
					bag_counter <= 9'd0;
					operate_state <= 5'd20;
				end
			end
			5'd18:begin			
				operate_state <= 5'd19;
				RD_FIFO_232 <= 1'b0;
				end
			5'd19:begin
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd17;
			end*/
			default:begin
				//data_to_ram_en <= 1'b0;//表示模块向RAM写数据完毕
				busy_flag <= 1'b0;//busy停止
				RAM_WE_ <= 1'b1;
				RD_FIFO_ONE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_TWO <= 1'b0;                  //收回读fifo信号
				RD_FIFO_THREE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_FORE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_232 <= 1'b0;                  //收回读fifo信号
				operate_state <= 5'd0;
			end
		endcase
		end
	endcase
	end//2
	
end//1
//====================================================================================================//
always @ (*)
begin
	if(  ((half_full_state == 1) && (busy_flag == 0))	||	((timer_start_flag == 1) && (busy_flag == 0))   ) begin
		next_state = 2'd1;//如果任意一路422半满并且busy==0，或者定时器计数到5ms并且busy==0，则触发下一状态==1
	end
	else 
	begin 
		if(busy_flag == 0) begin
			next_state = 2'd0;
		end
		else begin
			next_state = current_state;
		end
	end
end
//====================================================================================================//
//状态转换，将下一状态赋值给当前状态
always @(posedge CLK)
begin
    current_state <= next_state;
end
//====================================================================================================//
//定时器计数器
reg timer_start_flag;//定时器有效标志，当这一位有效，表示定时器计数到5ms，开始查询，高有效，低无效
parameter time_delay = 20'b10_0100_1111_1101_1011;//20'd151515 time = 151515*33ns = 4.999995ms
reg [19:0] timer;
always @ (posedge CLK or negedge reset_)
if (!reset_)begin
	timer <= 20'b0;
	timer_start_flag <= 1'b0;
end
else begin
	if(timer <= time_delay - 20'd1)begin
		timer <= timer + 20'b1;
	end
	else if(timer <= time_delay + 20'd1) begin
		if(busy_flag == 1'b1)begin//如果busy==1，表示正在工作，则如果计数器达到计数时间，则需要延迟数个周期
			timer <= timer;
			timer_start_flag <= 1'b1;
		end
		else begin
			timer <= timer + 20'b1;
			timer_start_flag <= 1'b1;
		end		
	end 
	else begin
		timer <= 20'd0;
		timer_start_flag <= 1'b0;
	end
end
//==================================================================================//
reg [14:0]read_bkfifo_counter;
reg [7:0] error_counter;
reg error_counter_enable;
always @(negedge CLK or negedge reset_)
begin
	if(!reset_)	begin
		TOTAL_NUM_be_readed <= 32'd0;
		read_bkfifo <= 1'b0;
		read_state <= 1'b0;
		read_bkfifo_counter <= 15'd0;
		error_counter_enable <= 1'b0;
		error_counter <= 8'd0;
	end
	else if(read_bkfifo_start) 
	begin 
		if(!read_bkfifo_counter[12]) begin
			case (read_state)
			1'b0:begin
				read_state <= 1'b1;
				read_bkfifo <= 1'b1;
				TOTAL_NUM_be_readed <= TOTAL_NUM_be_readed+32'd1;
				read_bkfifo_counter <= read_bkfifo_counter + 15'd1;
			end
			1'b1:begin
				read_state <= 1'b0;
				read_bkfifo <= 1'b0;
			end
			endcase
		end
		else begin
			read_bkfifo <= 1'b0;
			read_state <= 1'b0;
			error_counter_enable <= 1'b1;
		end		
	end
	else begin
		if(error_counter_enable)begin
			if(error_counter[5])begin
				read_bkfifo_counter <= 15'd0;
				error_counter_enable <= 1'b0;
			end
			else error_counter <= error_counter+ 8'd1;
		end
		else begin
			error_counter <= 8'd0;
		end
	end
	
end
assign read_bkfifo_request=((TOTAL_NUM_received - TOTAL_NUM_be_readed)>=32'd4096)? 1'b1:1'b0;
endmodule
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