core1.v

多功能卡的源代码

/*===============================================================================================*/
//刘通更改自core_controller
//注释时间：2009.3.9
//模块输入： 
	/*-----------------------------------------------------------------------------
		RHF_ONE_,		422第一路半满信号
		RFE_ONE_,			422第一路空信号
		     
		RHF_TWO_,                 422第二路半满信号 
		RFE_TWO_,                 422第二路空信号
		   
		RHF_THREE_,               422第三路半满信号
		RFE_THREE_,		422第三路空信号
		
		RHF_FORE_,		422第四路半满信号
		RFE_FORE_,		422第四路空信号
		-----------------------------------------------------------------
		RHF_232_,			232半满信号（本模块中暂时没用）
		RFE_232_,			232空信号（本模块中暂时没用）
		CLK,
		=======================================================
		read_bkfifo_start,	上端模块dma.v给的后端FIFO读信号
		reset_,			复位信号
		write_allow,			由后端FIFO引出的后端FIFO写允许信号，当后端FIFO存储空间大于等于256个时，
						此信号被拉低，此时允许往里写数据。
	----------------------------------------------------------*/
/*===============================================================================================*/
module core1(
		RHF_ONE_,   //422 channel one half full
		RFE_ONE_,                  //422第一路fifo读空
		RD_FIFO_ONE,               //读422第一路fifo控制信号
		RHF_TWO_,                  //422第一路fifo半满
		RFE_TWO_,                  //422第二路fifo读空
		RD_FIFO_TWO,               //读422第二路fifo控制信号
		RHF_THREE_,                //422第二路fifo半满
		RFE_THREE_,
		RD_FIFO_THREE,
		RHF_FORE_,
		RFE_FORE_,
		RD_FIFO_FORE,
		RHF_232_,
		RFE_232_,
		RD_FIFO_232,
		/////////////////////////////////////////////
		CLK,
		read_bkfifo_start,
		reset_,
		busy_flag,
		////////////////////////////////////////////
		write_allow,
		write_bkfifo,
		read_bkfifo,
		//OE_,
        ///////////////////////////////////////////
        //operate_state,
        dma_finish_flag,//DMA结束标志，LA写入该标志，表示此次DMA结束，清零地址寄存器
        //current_state,
        //RAM_WRITE_ADDR_POINTER,//输出给PCI总线的地址计数器的数值
		//RAM_READ_ADDR_POINTER,
        //data_to_ram_en,//如果各路fifo输出给ram的信号有效，则此位=1；否则此位==0
		//data_to_fifo_en,
        RAM_ADDR,
        RAM_OE_,
        RAM_CE1_,
        RAM_CE2,
        RAM_BHE_,
        RAM_BLE_,
        RAM_WE_,
		fifo_sel,
		//read_state,
		read_bkfifo_request,
		RAM_READ_ADDR_POINTER,
		RAM_WRITE_ADDR_POINTER);

input CLK;
input reset_;
input dma_finish_flag;
//422 and 232 FIFO控制和状态信号
input RHF_ONE_;                    //422第一路fifo半满
input RFE_ONE_;                    //422第一路fifo读空
output RD_FIFO_ONE;                //读422第一路fifo控制信号
reg RD_FIFO_ONE;

input RHF_TWO_;
input RFE_TWO_;
output RD_FIFO_TWO;
reg RD_FIFO_TWO;

input RHF_THREE_;
input RFE_THREE_;
output RD_FIFO_THREE;
reg RD_FIFO_THREE;

input RHF_FORE_;
input RFE_FORE_;
output RD_FIFO_FORE;
reg RD_FIFO_FORE;

input RHF_232_;
input RFE_232_;
output RD_FIFO_232;
reg RD_FIFO_232;

//RAM的控制信号
output RAM_CE1_;
output RAM_CE2;
output RAM_BHE_;
output RAM_BLE_;
output RAM_WE_;
output [19:0] RAM_ADDR;              //20bit width
reg RAM_CE1_;
reg RAM_CE2;
reg RAM_BHE_;
reg RAM_BLE_;
reg RAM_WE_;
reg [19:0] RAM_ADDR;              //20bit width
//===================================
output RAM_OE_;
reg RAM_OE_;
//===================================
//输出数据有效的标志
//output data_to_ram_en;
//reg data_to_ram_en;
//output data_to_fifo_en;
//reg data_to_fifo_en;
/////////////////////////////////////////////// 
reg [6:0] state;//bit 7 width
//繁忙标志信号，表示总线正在被占用
reg busy_flag;
output busy_flag;
/////////////////////////////////////

//地址计数器,用于地址对LD输出
reg [31:0] RAM_WRITE_ADDR_POINTER;
output [31:0] RAM_WRITE_ADDR_POINTER;
//读地址计数器，用于标志LD的DMA方式读到RAM的哪一个地址
reg [31:0] RAM_READ_ADDR_POINTER;
output [31:0] RAM_READ_ADDR_POINTER;
//output read_state;
reg read_state;//读后端FIFO用的状态机
reg write_state;//写后端FIFO用的状态机
//================================================================================================//
reg [1:0] current_state;
//output [1:0] current_state;
reg [1:0] next_state;
wire half_full_state;
assign half_full_state = RHF_ONE_ || RHF_TWO_ || RHF_THREE_ || RHF_FORE_ || RHF_232_;
reg [4:0] operate_state;
//output [4:0] operate_state;
/////////////////////////////////////
//output [31:0] TOTAL_NUM_received;
//output [31:0] TOTAL_NUM_be_readed;
reg [31:0] TOTAL_NUM_received;//已经接收的数据量，总共为4G
reg [31:0] TOTAL_NUM_be_readed;//已经被上位机读走的数据量
/////////////////////////////////////
//如果任意一路fifo半满，则half_full_state状态为0，表示半满，准备开始工作

input write_allow;
output write_bkfifo;
reg write_bkfifo;
/////////////////////////////////////
output [4:0]fifo_sel;
reg [4:0]fifo_sel;
//reg [3:0]read_once_counter;
reg [8:0]bag_counter;
////////////////////////////
input read_bkfifo_start;
output read_bkfifo;
reg read_bkfifo;

output read_bkfifo_request;
wire read_bkfifo_request;
/////////////////////////////////////
always @(negedge CLK or negedge reset_)
begin//1
	if(!reset_)begin
		RAM_BHE_ <= 1'b0;        //RAM_BHE_ is enable always
		RAM_BLE_ <= 1'b0;        //RAM_BLE_ is enable always
		RAM_OE_ <= 1'b1;
		RAM_WE_ <= 1'b1;
		RAM_CE1_ <= 1'b0;                     
		RAM_CE2 <= 1'b1;
		busy_flag <= 1'b0;
		
		RAM_WRITE_ADDR_POINTER <= 32'h0;//5地址计数器初始化
		operate_state <= 5'b00000;
		RAM_ADDR <= 20'h0;
		RAM_READ_ADDR_POINTER <= 32'h0;//5地址计数器初始化
		write_state <= 1'b0;
		//ds_7864fifo_rd <= 1'b1;
		//ds_7301fifo_rd <= 1'b1;
		RD_FIFO_ONE <= 1'b0;
		RD_FIFO_TWO <= 1'b0;
		RD_FIFO_THREE <= 1'b0;
		RD_FIFO_FORE <= 1'b0;
		RD_FIFO_232 <= 1'b0;

		//operate_state_readad1 <= 1'b0;
		//operate_state_readad2 <= 1'b0;
		//operate_state_read12io <= 1'b0;

		//data_to_ram_en <= 1'b0; 
		//data_to_fifo_en <= 1'b0;
		
		fifo_sel<=5'b11111;
		//read_once_counter<=4'd0;
		write_bkfifo <= 1'b0;
		bag_counter[8:0] <= 9'd0;
		
		TOTAL_NUM_received <= 32'd0;
	end
	else begin//2
		casex(current_state)
		2'd0:begin
			//busy_flag <= busy_flag;//没有任何处理 busy == 0
			if(busy_flag)	begin
				case (write_state)
				1'b0:	begin
					if(!bag_counter[8])	begin
					RAM_OE_ <= 1'b0;
					RAM_ADDR <= RAM_READ_ADDR_POINTER[19:0];//放入地址 
					RAM_READ_ADDR_POINTER <= RAM_READ_ADDR_POINTER + 32'd1;//计数器+1
					write_state <= 1'b1;
					write_bkfifo <= 1'b0;
					//RAM_CE1_ <= 1'b0;                     
					//RAM_CE2 <= 1'b1;
					end
					else begin
					write_bkfifo <= 1'b0;
					write_state <= 1'b0;
					busy_flag<=1'b0;
					RAM_OE_ <= 1'b1;
					//RAM_CE1_ <= 1'b1;                     
					//RAM_CE2 <= 1'b0;
					bag_counter <= 9'd0;
					//data_to_fifo_en <= 1'b0;
					end
				end
				1'b1:	begin
					write_bkfifo <= 1'b1;
					write_state <= 1'b0;
					bag_counter <= bag_counter+9'd1;
				end
				default:	begin
					write_bkfifo <= 1'b0;
					busy_flag<=1'b0;
					//RAM_OE_ <= 1'b1;
					//RAM_CE1_ <= 1'b1;                     
					//RAM_CE2 <= 1'b0;
					read_state <= 1'b0;
				end
				endcase
			end
			else if((busy_flag==1'b0)&&(!write_allow/*FIFO有8bit空余*/)&&(RAM_READ_ADDR_POINTER<RAM_WRITE_ADDR_POINTER/*RAM的读指针 小于 写指针*/) )
			//else if((busy_flag==1'b0)&&(!write_allow/*FIFO有8bit空余*/)&&(TOTAL_NUM_be_readed<TOTAL_NUM_received/*RAM的读指针 小于 写指针*/) )
			begin
				busy_flag <= 1'b1;
				//data_to_fifo_en <= 1'b1;
			end
			else begin
				busy_flag <= 1'b0;
				//data_to_fifo_en <= 1'b0;
			end
		end
	2'd1:begin//fifo半满了，从第一路到第四路，开始一次向ram里面写数据，然后地址自加一
		case(operate_state)
			5'd0:begin
				busy_flag <= 1'b1;
				//data_to_ram_en <= 1'b1;
				if(RHF_ONE_ == 1)begin//表示第一路是半满的情况
					operate_state <= 5'd1;//进入状态1
					fifo_sel[1]<=1'b0;//fifo选通
				end
				else if(RHF_TWO_ == 1)begin             
					operate_state <= 5'd5;
					fifo_sel[2]<=1'b0;
				end
				else if(RHF_THREE_ == 1)begin
					operate_state <= 5'd9;
					fifo_sel[3]<=1'b0;
				end
				else if(RHF_FORE_ == 1)begin     
					operate_state <= 5'd13; 
					fifo_sel[4]<=1'b0;
				end
				else begin
					//operate_state <= 5'd4;//进入第二通道
					operate_state<=5'd20;
				end
			end
			5'd1:begin
				if(!bag_counter[8])begin