ad7301_subctrl.v

多功能卡的源代码

/*
更改一：
	更改原因：
	更改内容 begin:
		1. ad7301_data <= {channel[2:0],ad7301_data_buf[12:0]};//刘通更改于2008.12.9 15：58
			这条语句没有用处删除（注释掉）
		2. else if(data_counter == 4'b1101 && channel == 3'b111&&else if(data_counter == 4'b1101 && channel == 3'b111&&operate_state ==5'b11111)//刘通 更改于2008.12.9 16：06)//刘通 更改于2008.12.9 16：06
			这条语句之前是else if(data_counter == 4'b1101 && channel == 3'b111) ，缺少上面的operate_state ==5'b11111判断，导致在第八个通道时，时间太短，出现了一个错误进入通道一的问题。
	end
*/
module ad7301_subctrl(reset,
				        SLOW_CLK,
						sample_start,
						SCLK,//shu chu ad xin pian dang zhong
						DOUT,//cong ad xin pian zhong hui du,shu ru dao FPGA zhong
						//ad7301_CS_,//shu chu ad xin pian dang zhong
						ad7301_data,//shu chu dao FIFO zhong
						fifo_write,
						//channel_cs,//tong dao xuan ze shu chu ,wai jie 138_coder
						channel,
						DIN,
						ad7301_data_buf
);

		input reset;              //0 is the bit of reset
		input SLOW_CLK;
		input sample_start;
		input DOUT;
		output DIN;
		output SCLK;
		
		//output ad7301_CS_;
		//reg ad7301_CS_;
		output [15:0] ad7301_data;
		output fifo_write;
		//output [7:0] channel_cs;
		output [15:0] ad7301_data_buf;
		output [2:0] channel;
		//wire [7:0] channel_cs;
		//reg block
		reg [15:0] ad7301_data;
		reg [4:0] operate_state;
		reg fifo_write;
		reg [2:0] channel;
		reg [3:0] data_counter;
		
		reg [15:0] ad7301_data_buf;
		reg DIN;
		reg SCLK;
		//reg SLOW_CLK;
		//code block
		//assign channel_cs = (channel == 3'b000)?8'b1111_1110:(channel == 3'b001)?8'b1111_1101:(channel == 3'b010)?8'b1111_1011:(channel == 3'b011)?8'b1111_0111:(channel == 3'b100)?8'b1110_1111:(channel == 3'b101)?8'b1101_1111:(channel == 3'b110)?8'b1011_1111:(channel == 3'b111)?8'b0111_1111:8'hzz;
		always @(posedge SLOW_CLK or negedge reset)
		begin
			if(!reset) begin
			DIN <= 1'b0;
			ad7301_data <= 16'h0;
			ad7301_data_buf <= 16'h0;
			operate_state <= 5'b00000;
			//ad7301_CS_ <= 1'b1;
			fifo_write <= 1'b0;
			//channel <= 3'b000;
			data_counter <= 4'b0;
			SCLK <= 1'b1;
			end
			else 
			begin
				if(!sample_start) begin
				case(operate_state)
					5'b00000:begin//0
					//ad7301_CS_ <= 1'b0;
					SCLK <= 1'b0;
					operate_state <= 5'b00001;
					ad7301_data_buf <= 16'h0;
					fifo_write <= 1'b0;
					end
					5'b00001:begin//1
					SCLK <= 1'b1;
					if(DOUT == 0)begin
						operate_state <= 5'b00010;
						end
					else begin
						//ad7301_CS_ <= 1'b1;
						operate_state <= 5'b00000;
						end
					end
					5'b00010:begin//2
					SCLK <=1'b0;
					operate_state <= 5'b00011;
					ad7301_data <= 16'h0;
					end
					5'b00011:begin//3
					SCLK <=1'b1;
					if(DOUT == 0)begin
						operate_state <= 5'b00100;
						end
					else begin
						//ad7301_CS_ <= 1'b1;
						operate_state <= 5'b00000;
						end
					end
					5'b00100:begin//4
					SCLK <=1'b0;
					operate_state <= 5'b00101;
					end
					5'b00101:begin//5
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD13
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b00110;
					end
					5'b00110:begin//6
					SCLK <= 1'b0;
					operate_state <= 5'b00111;
					end
					5'b00111:begin//7
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD12
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b01000;
					end
					5'b01000:begin//8
					SCLK <= 1'b0;
					operate_state <= 5'b01001;
					end
					5'b01001:begin//9
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD11
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b01010;
					end
					5'b01010:begin//10
					SCLK <= 1'b0;
					operate_state <= 5'b01011;
					end
					5'b01011:begin//11
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD10
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b01100;
					end
					5'b01100:begin//12
					SCLK <= 1'b0;
					operate_state <= 5'b01101;
					end
					5'b01101:begin//13
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD09
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b01110;
					end
					5'b01110:begin//14
					SCLK <= 1'b0;
					operate_state <= 5'b01111;
					end
					5'b01111:begin//15
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD08
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b10000;
					end
					5'b10000:begin//16
					SCLK <= 1'b0;
					operate_state <= 5'b10001;
					end
					5'b10001:begin//17
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD07
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b10010;
					end
					5'b10010:begin//18
					SCLK <= 1'b0;
					operate_state <= 5'b10011;
					end
					5'b10011:begin//19
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD06
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b10100;
					end
					5'b10100:begin//20
					SCLK <= 1'b0;
					operate_state <= 5'b10101;
					end
					5'b10101:begin//21
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD05
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b10110;
					end
					5'b10110:begin//22
					SCLK <= 1'b0;
					operate_state <= 5'b10111;
					end
					5'b10111:begin//23
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD04
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b11000;
					end
					5'b11000:begin//24
					SCLK <= 1'b0;
					operate_state <= 5'b11001;
					end
					5'b11001:begin//25
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD03
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b11010;
					end
					5'b11010:begin//26
					SCLK <= 1'b0;
					operate_state <= 5'b11011;
					end
					5'b11011:begin//27
					SCLK <= 1'b1;
					ad7301_data_buf <= {(ad7301_data_buf[14:0]),DOUT};//BD02
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b11100;
					end
					5'b11100:begin//28
					SCLK <= 1'b0;
					operate_state <= 5'b11101;
					end
					5'b11101:begin//29
					SCLK <= 1'b1;
					ad7301_data_buf <= {channel[2:0],(ad7301_data_buf[11:0]),DOUT};//BD01,this time data has been read 13 bits
					ad7301_data <= {channel[2:0],(ad7301_data_buf[11:0]),DOUT};
					data_counter <= data_counter + 4'd1;
					operate_state <= 5'b11110;
					end
					5'b11110:begin//30
					SCLK <= 1'b0;
					operate_state <= 5'b11111;
					end
					5'b11111:begin//31
					SCLK <= 1'b1;
					//ad7301_CS_ <= 1'b1;
					if(data_counter == 4'b1101) begin //start to write data to fifo
						//ad7301_data <= {channel[2:0],ad7301_data_buf[12:0]};//刘通更改于2008.12.9 15：58
						fifo_write <= 1'b1;
						data_counter <= 4'h0;
						operate_state <= 5'b00000;
						end
						else begin
						//ad7301_data <= ad7301_data_buf;
						//fifo_write <= 1'b1;
						data_counter <= 4'h0;
						operate_state <= 5'b00000;
						end
					end
					endcase
				end
				///////////////////////////////////////////////////////
				else 
				begin
					DIN <= 1'b0;
					ad7301_data <= 16'h0;
					ad7301_data_buf <= 16'h0;
					operate_state <= 5'b00000;
					//ad7301_CS_ <= 1'b1;
					fifo_write <= 1'b0;
					//channel <= 3'b000;
					data_counter <= 4'b0;
					SCLK <= 1'b1;
				end
			end
		end
		//////////////////////////////////////
/*			always @(posedge LCLK or negedge reset)
			begin
			if(!reset) begin
				channel <= 3'b000;
				end
			else begin
				if(data_counter == 4'b1101) begin
					if(channel < 3'b111)
						channel <= channel + 1;
					else
						channel <= 3'b000;
					end
				//end
				else begin
					channel <= channel;
					end
				end
			end*/
		always @(posedge SLOW_CLK or negedge reset)
		begin
			if(!reset) begin
				channel <= 3'b000;
				end
			else
				if(operate_state ==5'b11111 && data_counter == 4'b1101 && channel < 3'b111)
					channel <= channel + 3'd1;
				//else if(data_counter == 4'b1101 && channel == 3'b111)
				else if(data_counter == 4'b1101 && channel == 3'b111&&operate_state ==5'b11111)//刘通 更改于2008.12.9 16：06
					channel <= 3'b000;
				else
					channel <= channel;
		end
			//==========================================================================================//
endmodule