ad_test.tan.rpt

多功能卡的源代码

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Type                                                      ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                                                                                                                                     ; To                                                                                                                           ; From Clock                                 ; To Clock                                   ; Failed Paths ;
+-----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A       ; None                             ; 12.142 ns                                      ; LA[4]                                                                                                                                                                                    ; ad7864_fifo:inst7|ad7864_controller:inst4|fifo_data_buf[0]                                                                   ; --                                         ; CLK                                        ; 0            ;
; Worst-case tco                                            ; N/A       ; None                             ; 15.684 ns                                      ; ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|dpram_cg01:FIFOram|altsyncram_onj1:altsyncram1|ram_block2a6~portb_address_reg8 ; LD[5]                                                                                                                        ; CLK                                        ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A       ; None                             ; 19.926 ns                                      ; LA[4]                                                                                                                                                                                    ; LD[7]                                                                                                                        ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                             ; -1.391 ns                                      ; _232_sdin                                                                                                                                                                                ; _232_to_fifo:inst5|lt_uart_r5:inst6|in_count[0]                                                                              ; --                                         ; CLK                                        ; 0            ;
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk0' ; 1.489 ns  ; 66.00 MHz ( period = 15.151 ns ) ; N/A                                            ; dma:inst6|currentstate.s5                                                                                                                                                                ; core1:inst23|read_bkfifo_counter[1]                                                                                          ; altpll0:inst|altpll:altpll_component|_clk1 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLK'                                        ; 6.687 ns  ; 33.00 MHz ( period = 30.303 ns ) ; 59.07 MHz ( period = 16.928 ns )               ; _232_to_fifo:inst5|inst4                                                                                                                                                                 ; _232_to_fifo:inst5|inst3                                                                                                     ; CLK                                        ; CLK                                        ; 0            ;
; Clock Setup: 'altpll0:inst|altpll:altpll_component|_clk1' ; 28.701 ns ; 33.00 MHz ( period = 30.303 ns ) ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; dma:inst6|currentstate.s6                                                                                                                                                                ; dma:inst6|currentstate.s1                                                                                                    ; altpll0:inst|altpll:altpll_component|_clk1 ; altpll0:inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'CLK'                                         ; 0.578 ns  ; 33.00 MHz ( period = 30.303 ns ) ; N/A                                            ; _232_to_fifo:inst5|lt_uart_r5:inst6|d[7]                                                                                                                                                 ; _232_to_fifo:inst5|lt_uart_r5:inst6|data_out[0]                                                                              ; CLK                                        ; CLK                                        ; 0            ;
; Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk0'  ; 0.727 ns  ; 66.00 MHz ( period = 15.151 ns ) ; N/A                                            ; _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8]                                                             ; _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] ; altpll0:inst|altpll:altpll_component|_clk0 ; altpll0:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altpll0:inst|altpll:altpll_component|_clk1'  ; 0.933 ns  ; 33.00 MHz ( period = 30.303 ns ) ; N/A                                            ; dma:inst6|currentstate.s5                                                                                                                                                                ; dma:inst6|currentstate.s5                                                                                                    ; altpll0:inst|altpll:altpll_component|_clk1 ; altpll0:inst|altpll:altpll_component|_clk1 ; 0            ;
; Total number of failed paths                              ;           ;                                  ;                                                ;                                                                                                                                                                                          ;                                                                                                                              ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C6Q240C7        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;