ad_test.fit.qmsg

多功能卡的源代码

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "CLK " "Info: Promoted signal \"CLK\" to use global clock" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } { 0 "CLK" } } } } { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { -352 328 496 -336 "CLK" "" } { 592 -616 -544 608 "CLK" "" } } } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { CLK } } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0:inst\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll0:inst\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst\|altpll:altpll_component\|_clk0" } } } } { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { -408 528 784 -232 "inst" "" } } } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 590 3 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0:inst\|altpll:altpll_component\|_clk1 " "Info: Promoted signal \"altpll0:inst\|altpll:altpll_component\|_clk1\" to use global clock (user assigned)" {  } { { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst\|altpll:altpll_component\|_clk1" } } } } { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { -408 528 784 -232 "inst" "" } } } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 590 3 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0 "" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "_232_to_fifo:inst5\|clk_txd:inst1\|clk16x Global clock " "Info: Automatically promoted signal \"_232_to_fifo:inst5\|clk_txd:inst1\|clk16x\" to use Global clock" {  } { { "clk_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_txd.v" 7 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "7408:inst1\|4 Global clock " "Info: Automatically promoted some destinations of signal \"7408:inst1\|4\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "adt7301_fifo:inst26\|ad7301_controller:inst6\|work_ena~97 " "Info: Destination \"adt7301_fifo:inst26\|ad7301_controller:inst6\|work_ena~97\" may be non-global or may not use global clock" {  } { { "ad7301_controller.v" "" { Text "C:/Users/liutong/Desktop/CPCI/ad7301_controller.v" 34 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ad7864_fifo:inst7\|ad7864_controller:inst4\|fifo_data_buf\[11\]~219 " "Info: Destination \"ad7864_fifo:inst7\|ad7864_controller:inst4\|fifo_data_buf\[11\]~219\" may be non-global or may not use global clock" {  } { { "ad7864_controller.v" "" { Text "C:/Users/liutong/Desktop/CPCI/ad7864_controller.v" 205 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "7408:inst4\|4 " "Info: Destination \"7408:inst4\|4\" may be non-global or may not use global clock" {  } { { "7408.bdf" "" { Schematic "d:/altera/80/quartus/libraries/others/maxplus2/7408.bdf" { { 160 296 360 200 "4" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 0}  } { { "7408.bdf" "" { Schematic "d:/altera/80/quartus/libraries/others/maxplus2/7408.bdf" { { 160 296 360 200 "4" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "_422_to_fifo1:inst8\|14490:inst4\|7 Global clock " "Info: Automatically promoted signal \"_422_to_fifo1:inst8\|14490:inst4\|7\" to use Global clock" {  } { { "14490.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/14490.bdf" { { 256 208 272 296 "7" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "_422_to_fifo1:inst8\|14490:inst5\|7 Global clock " "Info: Automatically promoted signal \"_422_to_fifo1:inst8\|14490:inst5\|7\" to use Global clock" {  } { { "14490.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/14490.bdf" { { 256 208 272 296 "7" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "_422_to_fifo2:inst20\|14490:inst4\|7 Global clock " "Info: Automatically promoted signal \"_422_to_fifo2:inst20\|14490:inst4\|7\" to use Global clock" {  } { { "14490.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/14490.bdf" { { 256 208 272 296 "7" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}