ad_test.hif

多功能卡的源代码

9999
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
locked
-1
3
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
areset
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
d:|altera|80|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
d:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
d:|altera|80|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
d:|altera|80|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
}
# hierarchies {
altpll0:inst|altpll:altpll_component
}
# macro_sequence

# end
# entity
scfifo
# storage
db|ad_test.(19).cnf
db|ad_test.(19).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|megafunctions|scfifo.tdf
bd96886bec54cca1ebdbc8736bbb47
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
ON
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
256
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_ti61
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
d:|altera|80|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|altera|80|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
d:|altera|80|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|altera|80|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|altera|80|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
}
# hierarchies {
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component
}
# macro_sequence

# end
# entity
scfifo
# storage
db|ad_test.(39).cnf
db|ad_test.(39).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|megafunctions|scfifo.tdf
bd96886bec54cca1ebdbc8736bbb47
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
2048
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
11
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
1793
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_0s61
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
d:|altera|80|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|altera|80|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
d:|altera|80|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|altera|80|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|altera|80|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component
}
# macro_sequence

# end
# entity
scfifo
# storage
db|ad_test.(48).cnf
db|ad_test.(48).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|megafunctions|scfifo.tdf
bd96886bec54cca1ebdbc8736bbb47
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
256
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_p561
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
empty
-1
3
data
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
d:|altera|80|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|altera|80|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
d:|altera|80|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|altera|80|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|altera|80|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component
}
# macro_sequence

# end
# entity
scfifo
# storage
db|ad_test.(56).cnf
db|ad_test.(56).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|megafunctions|scfifo.tdf
bd96886bec54cca1ebdbc8736bbb47
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
256
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
8
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
128
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_ek61
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# include_file {
d:|altera|80|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
d:|altera|80|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
d:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
d:|altera|80|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
d:|altera|80|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
d:|altera|80|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component
}
# macro_sequence

# end
# entity
74138
# storage
db|ad_test.(58).cnf
db|ad_test.(58).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|others|maxplus2|74138.bdf
6cadbea2e3f85766eb8e4e262292077
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
adt7301_fifo:inst26|74138:inst
}
# macro_sequence

# end
# entity
core1
# storage
db|ad_test.(1).cnf
db|ad_test.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
core1.v
cb11de57388528ce11a349ace89d88c
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
time_delay
00100100111111011011
PARAMETER_UNSIGNED_BIN
USR
}
# hierarchies {
core1:inst23
}
# macro_sequence

# end
# entity
ad7864_fifo
# storage
db|ad_test.(37).cnf
db|ad_test.(37).cnf
# case_insensitive
# source_file
ad7864_fifo.bdf
32ef6724c4a449dec81e2d81c8c2d33
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
ad7864_fifo:inst7
}
# macro_sequence

# end
# entity
14490
# storage
db|ad_test.(2).cnf
db|ad_test.(2).cnf
# case_insensitive
# source_file
14490.bdf
d1fec64abab68af1b2eb96d4792cd18f
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_422_to_fifo1:inst8|14490:inst4
_422_to_fifo1:inst8|14490:inst5
_422_to_fifo2:inst20|14490:inst4
_422_to_fifo2:inst20|14490:inst5
_422_to_fifo3:inst21|14490:inst4
_422_to_fifo3:inst21|14490:inst5
_422_to_fifo4:inst22|14490:inst4
_422_to_fifo4:inst22|14490:inst5
}
# macro_sequence

# end
# entity
14491
# storage
db|ad_test.(11).cnf
db|ad_test.(11).cnf
# case_insensitive
# source_file
14491.bdf
84f43fa25220bb84dceda1c6dbeb780
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# macro_sequence

# end
# entity
CPCI_exp
# storage
db|ad_test.(30).cnf
db|ad_test.(30).cnf
# case_insensitive
# source_file
CPCI_exp.bdf
80aa99fc47deabd9fd52e95330f1631a
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
_422_to_fifo1
# storage
db|ad_test.(59).cnf
db|ad_test.(59).cnf
# case_insensitive
# source_file
_422_to_fifo1.bdf
aacf4542a7e5f0e6e996118f9ab7990
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_422_to_fifo1:inst8
}
# macro_sequence

# end
# entity
_422_receiver_2
# storage
db|ad_test.(61).cnf
db|ad_test.(61).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_422_receiver_2.v
f0bdfba6ec31c25545a75eb09fe6e5d1
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
_422_to_fifo1:inst8|_422_receiver_2:inst
_422_to_fifo2:inst20|_422_receiver_2:inst
_422_to_fifo3:inst21|_422_receiver_2:inst
_422_to_fifo4:inst22|_422_receiver_2:inst
}
# macro_sequence

# end
# entity
_422_to_fifo2
# storage
db|ad_test.(27).cnf
db|ad_test.(27).cnf
# case_insensitive
# source_file
_422_to_fifo2.bdf
51aa67693f5fbbbf504e22ee94c78874
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_422_to_fifo2:inst20
}
# macro_sequence

# end
# entity
_422_to_fifo3
# storage
db|ad_test.(28).cnf
db|ad_test.(28).cnf
# case_insensitive
# source_file
_422_to_fifo3.bdf
2abca56584652aa7465acaa7f6779afa
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_422_to_fifo3:inst21
}
# macro_sequence

# end
# entity
_422_to_fifo4
# storage
db|ad_test.(57).cnf
db|ad_test.(57).cnf
# case_insensitive
# source_file
_422_to_fifo4.bdf
501df7fed87f11838371364b276a4741
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_422_to_fifo4:inst22
}
# macro_sequence

# end
# complete