ad_test.hif

多功能卡的源代码

-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|dpram_cg01:FIFOram
}
# macro_sequence

# end
# entity
altsyncram_onj1
# storage
db|ad_test.(44).cnf
db|ad_test.(44).cnf
# case_insensitive
# source_file
db|altsyncram_onj1.tdf
f9328fecde8b62d55443bf2f367fd68
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|dpram_cg01:FIFOram|altsyncram_onj1:altsyncram1
}
# macro_sequence

# end
# entity
ad7864_controller
# storage
db|ad_test.(45).cnf
db|ad_test.(45).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ad7864_controller.v
ca74c52477698cce56ed0f917e12832
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
ad7864_fifo:inst7|ad7864_controller:inst4
}
# macro_sequence

# end
# entity
adt7301_fifo
# storage
db|ad_test.(46).cnf
db|ad_test.(46).cnf
# case_insensitive
# source_file
adt7301_fifo.bdf
d21110849fd7ad247392e8a155e4fde5
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
adt7301_fifo:inst26
}
# macro_sequence

# end
# entity
_7301fifo
# storage
db|ad_test.(47).cnf
db|ad_test.(47).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_7301fifo.v
6cbc47f48686b5a18e38cadb150362b
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1
}
# macro_sequence

# end
# entity
scfifo_ek61
# storage
db|ad_test.(49).cnf
db|ad_test.(49).cnf
# case_insensitive
# source_file
db|scfifo_ek61.tdf
864ac5873f5f89da3756993a3ebf89b
6
# used_port {
wrreq
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_tj31
# storage
db|ad_test.(50).cnf
db|ad_test.(50).cnf
# case_insensitive
# source_file
db|a_dpfifo_tj31.tdf
936ecc25dad1a44cd2de2eb87d3871
6
# used_port {
wreq
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo
}
# macro_sequence

# end
# entity
a_fefifo_08f
# storage
db|ad_test.(51).cnf
db|ad_test.(51).cnf
# case_insensitive
# source_file
db|a_fefifo_08f.tdf
277be2d02eba40bfa14acf58bac6e53
6
# used_port {
wreq
-1
3
usedw_out7
-1
3
usedw_out6
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|a_fefifo_08f:fifo_state
}
# macro_sequence

# end
# entity
cntr_bc7
# storage
db|ad_test.(52).cnf
db|ad_test.(52).cnf
# case_insensitive
# source_file
db|cntr_bc7.tdf
1dc0d1d2e39853cc7965ec732515bba
6
# used_port {
updown
-1
3
sclr
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|a_fefifo_08f:fifo_state|cntr_bc7:count_usedw
}
# macro_sequence

# end
# entity
dpram_bg01
# storage
db|ad_test.(53).cnf
db|ad_test.(53).cnf
# case_insensitive
# source_file
db|dpram_bg01.tdf
62c9ceb469f936addb8d89b68e26d4
6
# used_port {
wren
-1
3
wraddress7
-1
3
wraddress6
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress7
-1
3
rdaddress6
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|dpram_bg01:FIFOram
}
# macro_sequence

# end
# entity
altsyncram_mnj1
# storage
db|ad_test.(54).cnf
db|ad_test.(54).cnf
# case_insensitive
# source_file
db|altsyncram_mnj1.tdf
806b65111e65808197d4788792313bd
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|dpram_bg01:FIFOram|altsyncram_mnj1:altsyncram1
}
# macro_sequence

# end
# entity
ad7301_controller
# storage
db|ad_test.(55).cnf
db|ad_test.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ad7301_controller.v
ff244e82647ae8c414d9261ad4b3839
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
adt7301_fifo:inst26|ad7301_controller:inst6
}
# macro_sequence

# end
# entity
_422_receiver_1
# storage
db|ad_test.(26).cnf
db|ad_test.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_422_receiver_1.v
bbb1c41d3c2b54fd108e14271baca6db
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
scfifo
# storage
db|ad_test.(4).cnf
db|ad_test.(4).cnf
# case_insensitive
# source_file
d:|altera|80|quartus|libraries|megafunctions|scfifo.tdf
bd96886bec54cca1ebdbc8736bbb47
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
ON
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
256
PARAMETER_SIGNED_DEC
USR
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5