ad_test.hif

多功能卡的源代码

3
usedw10
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_mp31
# storage
db|ad_test.(32).cnf
db|ad_test.(32).cnf
# case_insensitive
# source_file
db|a_dpfifo_mp31.tdf
f8c5b7d52b218d677d4afec5ac266d3
6
# used_port {
wreq
-1
3
usedw9
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw10
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo
}
# macro_sequence

# end
# entity
altsyncram_71b1
# storage
db|ad_test.(33).cnf
db|ad_test.(33).cnf
# case_insensitive
# source_file
db|altsyncram_71b1.tdf
ac95f4beb6525c143f34842cb9fc06d
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo|altsyncram_71b1:FIFOram
}
# macro_sequence

# end
# entity
cntr_8db
# storage
db|ad_test.(34).cnf
db|ad_test.(34).cnf
# case_insensitive
# source_file
db|cntr_8db.tdf
7861d49c4f54619d3ebd9d7cdad7d31
6
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo|cntr_8db:rd_ptr_msb
}
# macro_sequence

# end
# entity
cntr_ld7
# storage
db|ad_test.(35).cnf
db|ad_test.(35).cnf
# case_insensitive
# source_file
db|cntr_ld7.tdf
c304f4979dc39da37cf9efcb0562077
6
# used_port {
updown
-1
3
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo|cntr_ld7:usedw_counter
}
# macro_sequence

# end
# entity
cntr_9db
# storage
db|ad_test.(36).cnf
db|ad_test.(36).cnf
# case_insensitive
# source_file
db|cntr_9db.tdf
ed6c386ae41b2fe03866ac775baac76
6
# used_port {
sclr
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_back_fifo:inst2|scfifo:scfifo_component|scfifo_0s61:auto_generated|a_dpfifo_mp31:dpfifo|cntr_9db:wr_ptr
}
# macro_sequence

# end
# entity
_7864fifo
# storage
db|ad_test.(38).cnf
db|ad_test.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_7864fifo.v
9f1898f4f92a16d7fa53a17159c4c919
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3
}
# macro_sequence

# end
# entity
scfifo_p561
# storage
db|ad_test.(40).cnf
db|ad_test.(40).cnf
# case_insensitive
# source_file
db|scfifo_p561.tdf
da42a5a7afb5a25411fdf0585f827b17
6
# used_port {
wrreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_6531
# storage
db|ad_test.(41).cnf
db|ad_test.(41).cnf
# case_insensitive
# source_file
db|a_dpfifo_6531.tdf
2953c65f6185f69e3de023ba892d4db8
6
# used_port {
wreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo
}
# macro_sequence

# end
# entity
a_fefifo_s7f
# storage
db|ad_test.(42).cnf
db|ad_test.(42).cnf
# case_insensitive
# source_file
db|a_fefifo_s7f.tdf
2e1a1323773a91cbe9d3d9994abb1a2a
6
# used_port {
wreq
-1
3
usedw_out8
-1
3
usedw_out7
-1
3
usedw_out6
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|a_fefifo_s7f:fifo_state
}
# macro_sequence

# end
# entity
dpram_cg01
# storage
db|ad_test.(43).cnf
db|ad_test.(43).cnf
# case_insensitive
# source_file
db|dpram_cg01.tdf
d1aadd27883bd7a4f414cc29b48c8
6
# used_port {
wren
-1
3
wraddress8
-1
3
wraddress7
-1
3
wraddress6
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress8
-1
3
rdaddress7
-1
3
rdaddress6
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3