ad_test.hif

多功能卡的源代码

Version 8.0 Build 215 05/29/2008 SJ Full Version
38
2466
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
CPCI_exp_bk
# storage
db|ad_test.(0).cnf
db|ad_test.(0).cnf
# case_insensitive
# source_file
CPCI_exp_bk.bdf
c2b3e03e6e757e76a7fb92466d8daa31
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# macro_sequence

# end
# entity
_422_fifo
# storage
db|ad_test.(3).cnf
db|ad_test.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_422_fifo.v
ad614a6f4fa5ac6b74b7b322348cfff
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3
_422_to_fifo2:inst20|_422_fifo:inst3
_422_to_fifo3:inst21|_422_fifo:inst3
_422_to_fifo4:inst22|_422_fifo:inst3
}
# macro_sequence

# end
# entity
scfifo_rl61
# storage
db|ad_test.(5).cnf
db|ad_test.(5).cnf
# case_insensitive
# source_file
db|scfifo_rl61.tdf
a19448f6f3e4c4d4418b04be94edfb
6
# used_port {
wrreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_8l31
# storage
db|ad_test.(6).cnf
db|ad_test.(6).cnf
# case_insensitive
# source_file
db|a_dpfifo_8l31.tdf
78b26e617074a8d30317b1a4bfe1073
6
# used_port {
wreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo
}
# macro_sequence

# end
# entity
altsyncram_boa1
# storage
db|ad_test.(7).cnf
db|ad_test.(7).cnf
# case_insensitive
# source_file
db|altsyncram_boa1.tdf
bf3e82cc1d23eb2bd981f3a8815cb3b3
6
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo|altsyncram_boa1:FIFOram
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|altsyncram_boa1:FIFOram
}
# macro_sequence

# end
# entity
cntr_vbb
# storage
db|ad_test.(8).cnf
db|ad_test.(8).cnf
# case_insensitive
# source_file
db|cntr_vbb.tdf
e91a08dbaf920a3fd822ebe2a0490
6
# used_port {
sclr
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_vbb:rd_ptr_msb
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo|cntr_vbb:rd_ptr_msb
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_vbb:rd_ptr_msb
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_vbb:rd_ptr_msb
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_vbb:rd_ptr_msb
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|cntr_vbb:rd_ptr_count
adt7301_fifo:inst26|_7301fifo:inst1|scfifo:scfifo_component|scfifo_ek61:auto_generated|a_dpfifo_tj31:dpfifo|cntr_vbb:wr_ptr
}
# macro_sequence

# end
# entity
cntr_cc7
# storage
db|ad_test.(9).cnf
db|ad_test.(9).cnf
# case_insensitive
# source_file
db|cntr_cc7.tdf
aa7826a59c4a7419648146e5feb4
6
# used_port {
updown
-1
3
sclr
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_cc7:usedw_counter
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo|cntr_cc7:usedw_counter
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_cc7:usedw_counter
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_cc7:usedw_counter
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_cc7:usedw_counter
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|a_fefifo_s7f:fifo_state|cntr_cc7:count_usedw
}
# macro_sequence

# end
# entity
cntr_0cb
# storage
db|ad_test.(10).cnf
db|ad_test.(10).cnf
# case_insensitive
# source_file
db|cntr_0cb.tdf
de364436ec3910fea8a9f6fd9233c7c7
6
# used_port {
sclr
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_0cb:wr_ptr
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo|cntr_0cb:wr_ptr
_422_to_fifo2:inst20|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_0cb:wr_ptr
_422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_0cb:wr_ptr
_422_to_fifo4:inst22|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|cntr_0cb:wr_ptr
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|cntr_0cb:rd_ptr_count
ad7864_fifo:inst7|_7864fifo:inst3|scfifo:scfifo_component|scfifo_p561:auto_generated|a_dpfifo_6531:dpfifo|cntr_0cb:wr_ptr
}
# macro_sequence

# end
# entity
dma
# storage
db|ad_test.(14).cnf
db|ad_test.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dma.v
81fdbdc0c767cb30bbc3abeac27b6c8a
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
s0
0000
PARAMETER_UNSIGNED_BIN
USR
s1
0001
PARAMETER_UNSIGNED_BIN
USR
s2
0010
PARAMETER_UNSIGNED_BIN
USR
s3
0011
PARAMETER_UNSIGNED_BIN
USR
s4
0100
PARAMETER_UNSIGNED_BIN
USR
s5
0101
PARAMETER_UNSIGNED_BIN
USR
s6
0110
PARAMETER_UNSIGNED_BIN
USR
}
# hierarchies {
dma:inst6
}
# macro_sequence

# end
# entity
altpll0
# storage
db|ad_test.(15).cnf
db|ad_test.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
altpll0.v
21d6b96b132ccadca15c191623fe7e34
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
altpll0:inst
}
# macro_sequence

# end
# entity
_232_to_fifo
# storage
db|ad_test.(17).cnf
db|ad_test.(17).cnf
# case_insensitive
# source_file
_232_to_fifo.bdf
649c724e85f02834cea3744fd5d5ff5b
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
_232_to_fifo:inst5
}
# macro_sequence

# end
# entity
_232_fifo
# storage
db|ad_test.(18).cnf
db|ad_test.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_232_fifo.v
71da2817c89144cce5b9bad0ff6bcc3e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
_232_to_fifo:inst5|_232_fifo:inst11
}
# macro_sequence

# end
# entity
scfifo_ti61
# storage
db|ad_test.(20).cnf
db|ad_test.(20).cnf
# case_insensitive
# source_file
db|scfifo_ti61.tdf
c8b27ba5312afd484f64e894a4ea6b
6
# used_port {
wrreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
almost_full
-1
3
aclr
-1
3
}
# hierarchies {
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated
}
# macro_sequence

# end
# entity
a_dpfifo_ai31
# storage
db|ad_test.(21).cnf
db|ad_test.(21).cnf
# case_insensitive
# source_file
db|a_dpfifo_ai31.tdf
79e2e8cb1b3f1f255ca2c28830d6921a
6
# used_port {
wreq
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
_232_to_fifo:inst5|_232_fifo:inst11|scfifo:scfifo_component|scfifo_ti61:auto_generated|a_dpfifo_ai31:dpfifo
}
# macro_sequence

# end
# entity
lt_uart_r5
# storage
db|ad_test.(22).cnf
db|ad_test.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lt_uart_r5.v
45f7611166445b24ff9a9f23fd1a90e3
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
_232_to_fifo:inst5|lt_uart_r5:inst6
}
# macro_sequence

# end
# entity
clk_txd
# storage
db|ad_test.(23).cnf
db|ad_test.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clk_txd.v
ec79838e885595e77d8f91a44d87227e
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
f_data1
54
PARAMETER_SIGNED_DEC
DEF
f_data2
108
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
_232_to_fifo:inst5|clk_txd:inst1
}
# macro_sequence

# end
# entity
_422_txd1
# storage
db|ad_test.(24).cnf
db|ad_test.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_422_txd1.v
6a1d38f81851fba3925c9f7f1a6c030
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
_422_txd_power
# storage
db|ad_test.(25).cnf
db|ad_test.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_422_txd_power.v
2f48609b873f27b8830cfee67e6d296
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# macro_sequence

# end
# entity
_back_fifo
# storage
db|ad_test.(29).cnf
db|ad_test.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
_back_fifo.v
b08461af27547daa7fb51e51a6b2c64
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
_back_fifo:inst2
}
# macro_sequence

# end
# entity
scfifo_0s61
# storage
db|ad_test.(31).cnf
db|ad_test.(31).cnf
# case_insensitive
# source_file
db|scfifo_0s61.tdf
3940cf5f471fbebef57d9a5adad59522
6
# used_port {
wrreq
-1
3
usedw9
-1
3
usedw8
-1
3
usedw7
-1
3
usedw6
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1