ad_test.hier_info

多功能卡的源代码

clock => counter_cella8.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB
cnt_en => counter_cella7.DATAB
cnt_en => counter_cella8.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
sclr => counter_cella5.SCLR
sclr => counter_cella6.SCLR
sclr => counter_cella7.SCLR
sclr => counter_cella8.SCLR


|CPCI_exp|_422_to_fifo1:inst8|_422_receiver_2:inst
reset => data_receive_begin.ACLR
reset => bit_counter[0].ACLR
reset => bit_counter[1].ACLR
reset => bit_counter[2].ACLR
reset => data[0].ACLR
reset => data[1].ACLR
reset => data[2].ACLR
reset => data[3].ACLR
reset => data[4].ACLR
reset => data[5].ACLR
reset => data[6].ACLR
reset => data[7].ACLR
reset => dout[7]~reg0.ACLR
reset => dout[6]~reg0.ACLR
reset => dout[5]~reg0.ACLR
reset => dout[4]~reg0.ACLR
reset => dout[3]~reg0.ACLR
reset => dout[2]~reg0.ACLR
reset => dout[1]~reg0.ACLR
reset => dout[0]~reg0.ACLR
reset => wrn~reg0.ACLR
reset => state~5.IN1
sdin => sdin_reg1.DATAIN
sys_clock => sclk_reg1.CLK
sys_clock => sclk_reg2.CLK
sys_clock => sdin_reg1.CLK
sys_clock => data[7].CLK
sys_clock => data[6].CLK
sys_clock => data[5].CLK
sys_clock => data[4].CLK
sys_clock => data[3].CLK
sys_clock => data[2].CLK
sys_clock => data[1].CLK
sys_clock => data[0].CLK
sys_clock => bit_counter[2].CLK
sys_clock => bit_counter[1].CLK
sys_clock => bit_counter[0].CLK
sys_clock => data_receive_begin.CLK
sys_clock => dout[7]~reg0.CLK
sys_clock => dout[6]~reg0.CLK
sys_clock => dout[5]~reg0.CLK
sys_clock => dout[4]~reg0.CLK
sys_clock => dout[3]~reg0.CLK
sys_clock => dout[2]~reg0.CLK
sys_clock => dout[1]~reg0.CLK
sys_clock => dout[0]~reg0.CLK
sys_clock => wrn~reg0.CLK
sys_clock => state~4.IN1
sclk => sclk_reg1.DATAIN
r_enable => data_receive_begin~1.OUTPUTSELECT
r_enable => bit_counter~5.OUTPUTSELECT
r_enable => bit_counter~4.OUTPUTSELECT
r_enable => bit_counter~3.OUTPUTSELECT
r_enable => data~15.OUTPUTSELECT
r_enable => data~14.OUTPUTSELECT
r_enable => data~13.OUTPUTSELECT
r_enable => data~12.OUTPUTSELECT
r_enable => data~11.OUTPUTSELECT
r_enable => data~10.OUTPUTSELECT
r_enable => data~9.OUTPUTSELECT
r_enable => data~8.OUTPUTSELECT
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wrn <= wrn~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CPCI_exp|_422_to_fifo1:inst8|14490:inst4
D5 <= 20.DB_MAX_OUTPUT_PORT_TYPE
CLK => 26.IN0
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
D0 => 7.IN1
D0 => 16.DATAIN


|CPCI_exp|_422_to_fifo1:inst8|14490:inst5
D5 <= 20.DB_MAX_OUTPUT_PORT_TYPE
CLK => 26.IN0
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
D0 => 7.IN1
D0 => 16.DATAIN


|CPCI_exp|_422_to_fifo1:inst8|74541:inst7
Y7 <= 26.DB_MAX_OUTPUT_PORT_TYPE
A7 => 26.DATAIN
GN1 => 2.IN0
GN2 => 2.IN1
Y8 <= 24.DB_MAX_OUTPUT_PORT_TYPE
A8 => 24.DATAIN
Y6 <= 19.DB_MAX_OUTPUT_PORT_TYPE
A6 => 19.DATAIN
Y5 <= 17.DB_MAX_OUTPUT_PORT_TYPE
A5 => 17.DATAIN
Y3 <= 14.DB_MAX_OUTPUT_PORT_TYPE
A3 => 14.DATAIN
Y4 <= 12.DB_MAX_OUTPUT_PORT_TYPE
A4 => 12.DATAIN
Y2 <= 7.DB_MAX_OUTPUT_PORT_TYPE
A2 => 7.DATAIN
Y1 <= 5.DB_MAX_OUTPUT_PORT_TYPE
A1 => 5.DATAIN


|CPCI_exp|_422_to_fifo1:inst8|74541:inst8
Y7 <= 26.DB_MAX_OUTPUT_PORT_TYPE
A7 => 26.DATAIN
GN1 => 2.IN0
GN2 => 2.IN1
Y8 <= 24.DB_MAX_OUTPUT_PORT_TYPE
A8 => 24.DATAIN
Y6 <= 19.DB_MAX_OUTPUT_PORT_TYPE
A6 => 19.DATAIN
Y5 <= 17.DB_MAX_OUTPUT_PORT_TYPE
A5 => 17.DATAIN
Y3 <= 14.DB_MAX_OUTPUT_PORT_TYPE
A3 => 14.DATAIN
Y4 <= 12.DB_MAX_OUTPUT_PORT_TYPE
A4 => 12.DATAIN
Y2 <= 7.DB_MAX_OUTPUT_PORT_TYPE
A2 => 7.DATAIN
Y1 <= 5.DB_MAX_OUTPUT_PORT_TYPE
A1 => 5.DATAIN


|CPCI_exp|7408:inst1
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|CPCI_exp|dma:inst6
CLK => LHOLDA~reg0.CLK
CLK => currentstate~0.IN1
LA[2] => Equal0.IN0
LA[2] => Equal1.IN3
LA[2] => Equal2.IN0
LA[2] => Equal3.IN2
LA[2] => Equal4.IN0
LA[2] => Equal5.IN0
LA[2] => Equal6.IN2
LA[2] => Equal7.IN0
LA[2] => Equal8.IN1
LA[2] => Equal9.IN2
LA[2] => Equal10.IN2
LA[2] => Equal11.IN0
LA[3] => Equal0.IN1
LA[3] => Equal1.IN4
LA[3] => Equal2.IN1
LA[3] => Equal3.IN0
LA[3] => Equal4.IN1
LA[3] => Equal5.IN2
LA[3] => Equal6.IN0
LA[3] => Equal7.IN1
LA[3] => Equal8.IN2
LA[3] => Equal9.IN0
LA[3] => Equal10.IN0
LA[3] => Equal11.IN1
LA[4] => Equal0.IN2
LA[4] => Equal1.IN0
LA[4] => Equal2.IN5
LA[4] => Equal3.IN3
LA[4] => Equal4.IN3
LA[4] => Equal5.IN3
LA[4] => Equal6.IN3
LA[4] => Equal7.IN3
LA[4] => Equal8.IN3
LA[4] => Equal9.IN3
LA[4] => Equal10.IN1
LA[4] => Equal11.IN2
LA[5] => Equal0.IN3
LA[5] => Equal1.IN5
LA[5] => Equal2.IN2
LA[5] => Equal3.IN1
LA[5] => Equal4.IN4
LA[5] => Equal5.IN4
LA[5] => Equal6.IN4
LA[5] => Equal7.IN4
LA[5] => Equal8.IN4
LA[5] => Equal9.IN4
LA[5] => Equal10.IN3
LA[5] => Equal11.IN3
LA[6] => Equal0.IN4
LA[6] => Equal1.IN1
LA[6] => Equal2.IN3
LA[6] => Equal3.IN4
LA[6] => Equal4.IN2
LA[6] => Equal5.IN1
LA[6] => Equal6.IN1
LA[6] => Equal7.IN5
LA[6] => Equal8.IN5
LA[6] => Equal9.IN5
LA[6] => Equal10.IN4
LA[6] => Equal11.IN4
LA[7] => Equal0.IN5
LA[7] => Equal1.IN2
LA[7] => Equal2.IN4
LA[7] => Equal3.IN5
LA[7] => Equal4.IN5
LA[7] => Equal5.IN5
LA[7] => Equal6.IN5
LA[7] => Equal7.IN2
LA[7] => Equal8.IN0
LA[7] => Equal9.IN1
LA[7] => Equal10.IN5
LA[7] => Equal11.IN5
LA[8] => ~NO_FANOUT~
LA[9] => ~NO_FANOUT~
LD[0] <= LD[0]~22
LD[0] <= LD[0]~32
LD[0] <= LD[0]~64
LD[1] <= LD[1]~21
LD[1] <= LD[1]~33
LD[1] <= LD[1]~65
LD[2] <= LD[2]~20
LD[2] <= LD[2]~34
LD[2] <= LD[2]~66
LD[3] <= LD[3]~19
LD[3] <= LD[3]~35
LD[3] <= LD[3]~67
LD[4] <= LD[4]~18
LD[4] <= LD[4]~36
LD[4] <= LD[4]~68
LD[5] <= LD[5]~17
LD[5] <= LD[5]~37
LD[5] <= LD[5]~69
LD[6] <= LD[6]~16
LD[6] <= LD[6]~38
LD[6] <= LD[6]~70
LD[7] <= LD[7]~15
LD[7] <= LD[7]~39
LD[7] <= LD[7]~71
LD[8] <= LD[8]~14
LD[8] <= LD[8]~40
LD[8] <= LD[8]~72
LD[9] <= LD[9]~13
LD[9] <= LD[9]~41
LD[9] <= LD[9]~73
LD[10] <= LD[10]~12
LD[10] <= LD[10]~42
LD[10] <= LD[10]~74
LD[11] <= LD[11]~11
LD[11] <= LD[11]~43
LD[11] <= LD[11]~75
LD[12] <= LD[12]~10
LD[12] <= LD[12]~44
LD[12] <= LD[12]~76
LD[13] <= LD[13]~9
LD[13] <= LD[13]~45
LD[13] <= LD[13]~77
LD[14] <= LD[14]~8
LD[14] <= LD[14]~46
LD[14] <= LD[14]~78
LD[15] <= LD[15]~7
LD[15] <= LD[15]~47
LD[15] <= LD[15]~79
LD[16] <= LD[16]~6
LD[16] <= LD[16]~48
LD[16] <= LD[16]~80
LD[17] <= LD[17]~5
LD[17] <= LD[17]~49
LD[17] <= LD[17]~81
LD[18] <= LD[18]~4
LD[18] <= LD[18]~50
LD[18] <= LD[18]~82
LD[19] <= LD[19]~3
LD[19] <= LD[19]~51
LD[19] <= LD[19]~83
LD[20] <= LD[20]~2
LD[20] <= LD[20]~52
LD[20] <= LD[20]~84
LD[21] <= LD[21]~1
LD[21] <= LD[21]~53
LD[21] <= LD[21]~85
LD[22] <= LD[22]~0
LD[22] <= LD[22]~54
LD[22] <= LD[22]~86
LD[23] <= LD[23]~23
LD[23] <= LD[23]~55
LD[23] <= LD[23]~87
LD[24] <= LD[24]~24
LD[24] <= LD[24]~56
LD[24] <= LD[24]~88
LD[25] <= LD[25]~25
LD[25] <= LD[25]~57
LD[25] <= LD[25]~89
LD[26] <= LD[26]~26
LD[26] <= LD[26]~58
LD[26] <= LD[26]~90
LD[27] <= LD[27]~27
LD[27] <= LD[27]~59
LD[27] <= LD[27]~91
LD[28] <= LD[28]~28
LD[28] <= LD[28]~60
LD[28] <= LD[28]~92
LD[29] <= LD[29]~29
LD[29] <= LD[29]~61
LD[29] <= LD[29]~93
LD[30] <= LD[30]~30
LD[30] <= LD[30]~62
LD[30] <= LD[30]~94
LD[31] <= LD[31]~31
LD[31] <= LD[31]~63
LD[31] <= LD[31]~95
LHOLD => LHOLDA~reg0.DATAIN
LHOLDA <= LHOLDA~reg0.DB_MAX_OUTPUT_PORT_TYPE
LWR => read_bkfifo_request~1.IN0
LWR => rd_232_direct~1.IN0
LWR => _19200_sel~1.IN0
LWR => _9600_sel~1.IN0
LWR => rd_12channel_io~1.IN0
LWR => rd_7301_fifo~1.IN0
LWR => rd_7864_fifo~1.IN0
LWR => read_bkfifo_start~1.IN0
LWR => LD~129.IN0