ad_test.hier_info

多功能卡的源代码

reset_ => RAM_ADDR[17]~reg0.ACLR
reset_ => RAM_ADDR[16]~reg0.ACLR
reset_ => RAM_ADDR[15]~reg0.ACLR
reset_ => RAM_ADDR[14]~reg0.ACLR
reset_ => RAM_ADDR[13]~reg0.ACLR
reset_ => RAM_ADDR[12]~reg0.ACLR
reset_ => RAM_ADDR[11]~reg0.ACLR
reset_ => RAM_ADDR[10]~reg0.ACLR
reset_ => RAM_ADDR[9]~reg0.ACLR
reset_ => RAM_ADDR[8]~reg0.ACLR
reset_ => RAM_ADDR[7]~reg0.ACLR
reset_ => RAM_ADDR[6]~reg0.ACLR
reset_ => RAM_ADDR[5]~reg0.ACLR
reset_ => RAM_ADDR[4]~reg0.ACLR
reset_ => RAM_ADDR[3]~reg0.ACLR
reset_ => RAM_ADDR[2]~reg0.ACLR
reset_ => RAM_ADDR[1]~reg0.ACLR
reset_ => RAM_ADDR[0]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[31]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[30]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[29]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[28]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[27]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[26]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[25]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[24]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[23]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[22]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[21]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[20]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[19]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[18]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[17]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[16]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[15]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[14]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[13]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[12]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[11]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[10]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[9]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[8]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[7]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[6]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[5]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[4]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[3]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[2]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[1]~reg0.ACLR
reset_ => RAM_READ_ADDR_POINTER[0]~reg0.ACLR
reset_ => write_state.ACLR
reset_ => RD_FIFO_ONE~reg0.ACLR
reset_ => RD_FIFO_TWO~reg0.ACLR
reset_ => RD_FIFO_THREE~reg0.ACLR
reset_ => RD_FIFO_FORE~reg0.ACLR
reset_ => RD_FIFO_232~reg0.ACLR
reset_ => fifo_sel[4]~reg0.PRESET
reset_ => fifo_sel[3]~reg0.PRESET
reset_ => fifo_sel[2]~reg0.PRESET
reset_ => fifo_sel[1]~reg0.PRESET
reset_ => write_bkfifo~reg0.ACLR
reset_ => bag_counter[8].ACLR
reset_ => bag_counter[7].ACLR
reset_ => bag_counter[6].ACLR
reset_ => bag_counter[5].ACLR
reset_ => bag_counter[4].ACLR
reset_ => bag_counter[3].ACLR
reset_ => bag_counter[2].ACLR
reset_ => bag_counter[1].ACLR
reset_ => bag_counter[0].ACLR
reset_ => TOTAL_NUM_received[31].ACLR
reset_ => TOTAL_NUM_received[30].ACLR
reset_ => TOTAL_NUM_received[29].ACLR
reset_ => TOTAL_NUM_received[28].ACLR
reset_ => TOTAL_NUM_received[27].ACLR
reset_ => TOTAL_NUM_received[26].ACLR
reset_ => TOTAL_NUM_received[25].ACLR
reset_ => TOTAL_NUM_received[24].ACLR
reset_ => TOTAL_NUM_received[23].ACLR
reset_ => TOTAL_NUM_received[22].ACLR
reset_ => TOTAL_NUM_received[21].ACLR
reset_ => TOTAL_NUM_received[20].ACLR
reset_ => TOTAL_NUM_received[19].ACLR
reset_ => TOTAL_NUM_received[18].ACLR
reset_ => TOTAL_NUM_received[17].ACLR
reset_ => TOTAL_NUM_received[16].ACLR
reset_ => TOTAL_NUM_received[15].ACLR
reset_ => TOTAL_NUM_received[14].ACLR
reset_ => TOTAL_NUM_received[13].ACLR
reset_ => TOTAL_NUM_received[12].ACLR
reset_ => TOTAL_NUM_received[11].ACLR
reset_ => TOTAL_NUM_received[10].ACLR
reset_ => TOTAL_NUM_received[9].ACLR
reset_ => TOTAL_NUM_received[8].ACLR
reset_ => TOTAL_NUM_received[7].ACLR
reset_ => TOTAL_NUM_received[6].ACLR
reset_ => TOTAL_NUM_received[5].ACLR
reset_ => TOTAL_NUM_received[4].ACLR
reset_ => TOTAL_NUM_received[3].ACLR
reset_ => TOTAL_NUM_received[2].ACLR
reset_ => TOTAL_NUM_received[1].ACLR
reset_ => TOTAL_NUM_received[0].ACLR
reset_ => operate_state~24.IN1
busy_flag <= busy_flag~reg0.DB_MAX_OUTPUT_PORT_TYPE
write_allow => always0~0.IN1
write_bkfifo <= write_bkfifo~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_bkfifo <= read_bkfifo~reg0.DB_MAX_OUTPUT_PORT_TYPE
dma_finish_flag => ~NO_FANOUT~
RAM_ADDR[0] <= RAM_ADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[1] <= RAM_ADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[2] <= RAM_ADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[3] <= RAM_ADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[4] <= RAM_ADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[5] <= RAM_ADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[6] <= RAM_ADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[7] <= RAM_ADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[8] <= RAM_ADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[9] <= RAM_ADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[10] <= RAM_ADDR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[11] <= RAM_ADDR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[12] <= RAM_ADDR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[13] <= RAM_ADDR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[14] <= RAM_ADDR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[15] <= RAM_ADDR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[16] <= RAM_ADDR[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[17] <= RAM_ADDR[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[18] <= RAM_ADDR[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_ADDR[19] <= RAM_ADDR[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_OE_ <= RAM_OE_~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_CE1_ <= <GND>
RAM_CE2 <= <VCC>
RAM_BHE_ <= <GND>
RAM_BLE_ <= <GND>
RAM_WE_ <= RAM_WE_~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_sel[0] <= <VCC>
fifo_sel[1] <= fifo_sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_sel[2] <= fifo_sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_sel[3] <= fifo_sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifo_sel[4] <= fifo_sel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_bkfifo_request <= LessThan3.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[0] <= RAM_READ_ADDR_POINTER[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[1] <= RAM_READ_ADDR_POINTER[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[2] <= RAM_READ_ADDR_POINTER[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[3] <= RAM_READ_ADDR_POINTER[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[4] <= RAM_READ_ADDR_POINTER[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[5] <= RAM_READ_ADDR_POINTER[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[6] <= RAM_READ_ADDR_POINTER[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[7] <= RAM_READ_ADDR_POINTER[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[8] <= RAM_READ_ADDR_POINTER[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[9] <= RAM_READ_ADDR_POINTER[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[10] <= RAM_READ_ADDR_POINTER[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[11] <= RAM_READ_ADDR_POINTER[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[12] <= RAM_READ_ADDR_POINTER[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[13] <= RAM_READ_ADDR_POINTER[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[14] <= RAM_READ_ADDR_POINTER[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[15] <= RAM_READ_ADDR_POINTER[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[16] <= RAM_READ_ADDR_POINTER[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[17] <= RAM_READ_ADDR_POINTER[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[18] <= RAM_READ_ADDR_POINTER[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[19] <= RAM_READ_ADDR_POINTER[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[20] <= RAM_READ_ADDR_POINTER[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[21] <= RAM_READ_ADDR_POINTER[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[22] <= RAM_READ_ADDR_POINTER[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[23] <= RAM_READ_ADDR_POINTER[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[24] <= RAM_READ_ADDR_POINTER[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[25] <= RAM_READ_ADDR_POINTER[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[26] <= RAM_READ_ADDR_POINTER[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[27] <= RAM_READ_ADDR_POINTER[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[28] <= RAM_READ_ADDR_POINTER[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[29] <= RAM_READ_ADDR_POINTER[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[30] <= RAM_READ_ADDR_POINTER[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_READ_ADDR_POINTER[31] <= RAM_READ_ADDR_POINTER[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[0] <= RAM_WRITE_ADDR_POINTER[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[1] <= RAM_WRITE_ADDR_POINTER[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[2] <= RAM_WRITE_ADDR_POINTER[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[3] <= RAM_WRITE_ADDR_POINTER[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[4] <= RAM_WRITE_ADDR_POINTER[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[5] <= RAM_WRITE_ADDR_POINTER[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[6] <= RAM_WRITE_ADDR_POINTER[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[7] <= RAM_WRITE_ADDR_POINTER[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[8] <= RAM_WRITE_ADDR_POINTER[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[9] <= RAM_WRITE_ADDR_POINTER[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[10] <= RAM_WRITE_ADDR_POINTER[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[11] <= RAM_WRITE_ADDR_POINTER[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[12] <= RAM_WRITE_ADDR_POINTER[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[13] <= RAM_WRITE_ADDR_POINTER[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[14] <= RAM_WRITE_ADDR_POINTER[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[15] <= RAM_WRITE_ADDR_POINTER[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[16] <= RAM_WRITE_ADDR_POINTER[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[17] <= RAM_WRITE_ADDR_POINTER[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[18] <= RAM_WRITE_ADDR_POINTER[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[19] <= RAM_WRITE_ADDR_POINTER[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[20] <= RAM_WRITE_ADDR_POINTER[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[21] <= RAM_WRITE_ADDR_POINTER[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[22] <= RAM_WRITE_ADDR_POINTER[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[23] <= RAM_WRITE_ADDR_POINTER[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[24] <= RAM_WRITE_ADDR_POINTER[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[25] <= RAM_WRITE_ADDR_POINTER[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[26] <= RAM_WRITE_ADDR_POINTER[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[27] <= RAM_WRITE_ADDR_POINTER[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[28] <= RAM_WRITE_ADDR_POINTER[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[29] <= RAM_WRITE_ADDR_POINTER[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[30] <= RAM_WRITE_ADDR_POINTER[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RAM_WRITE_ADDR_POINTER[31] <= RAM_WRITE_ADDR_POINTER[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CPCI_exp|_422_to_fifo1:inst8
half_full <= _422_fifo:inst3.almost_full
reset => inst1.ACLR
reset => _422_receiver_2:inst.reset
reset => 28.IN0
clock => 27.IN0
clock => 14490:inst4.CLK
clock => _422_receiver_2:inst.sys_clock
clock => 14490:inst5.CLK
clock => _422_fifo:inst3.clock
sdin => 14490:inst4.D0
sclk => 14490:inst5.D0
r_enable => _422_receiver_2:inst.r_enable
readn => _422_fifo:inst3.rdreq
empty <= _422_fifo:inst3.empty
fifo_out[0] <= 74541:inst7.Y1
fifo_out[1] <= 74541:inst7.Y2
fifo_out[2] <= 74541:inst7.Y3
fifo_out[3] <= 74541:inst7.Y4
fifo_out[4] <= 74541:inst7.Y5
fifo_out[5] <= 74541:inst7.Y6
fifo_out[6] <= 74541:inst7.Y7
fifo_out[7] <= 74541:inst7.Y8
fifo_out[8] <= 74541:inst8.Y1
fifo_out[9] <= 74541:inst8.Y2
fifo_out[10] <= 74541:inst8.Y3
fifo_out[11] <= 74541:inst8.Y4
fifo_out[12] <= 74541:inst8.Y5
fifo_out[13] <= 74541:inst8.Y6
fifo_out[14] <= 74541:inst8.Y7
fifo_out[15] <= 74541:inst8.Y8
/OE => 74541:inst7.GN2
/OE => 74541:inst7.GN1
/OE => 74541:inst8.GN2
/OE => 74541:inst8.GN1


|CPCI_exp|_422_to_fifo1:inst8|_422_fifo:inst3
aclr => aclr~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdreq => rdreq~0.IN1
wrreq => wrreq~0.IN1
almost_full <= scfifo:scfifo_component.almost_full
empty <= scfifo:scfifo_component.empty
full <= scfifo:scfifo_component.full
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
usedw[0] <= scfifo:scfifo_component.usedw
usedw[1] <= scfifo:scfifo_component.usedw
usedw[2] <= scfifo:scfifo_component.usedw
usedw[3] <= scfifo:scfifo_component.usedw
usedw[4] <= scfifo:scfifo_component.usedw
usedw[5] <= scfifo:scfifo_component.usedw
usedw[6] <= scfifo:scfifo_component.usedw
usedw[7] <= scfifo:scfifo_component.usedw
usedw[8] <= scfifo:scfifo_component.usedw


|CPCI_exp|_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component
data[0] => scfifo_rl61:auto_generated.data[0]
data[1] => scfifo_rl61:auto_generated.data[1]
data[2] => scfifo_rl61:auto_generated.data[2]
data[3] => scfifo_rl61:auto_generated.data[3]
data[4] => scfifo_rl61:auto_generated.data[4]
data[5] => scfifo_rl61:auto_generated.data[5]
data[6] => scfifo_rl61:auto_generated.data[6]
data[7] => scfifo_rl61:auto_generated.data[7]
q[0] <= scfifo_rl61:auto_generated.q[0]
q[1] <= scfifo_rl61:auto_generated.q[1]
q[2] <= scfifo_rl61:auto_generated.q[2]
q[3] <= scfifo_rl61:auto_generated.q[3]
q[4] <= scfifo_rl61:auto_generated.q[4]
q[5] <= scfifo_rl61:auto_generated.q[5]
q[6] <= scfifo_rl61:auto_generated.q[6]
q[7] <= scfifo_rl61:auto_generated.q[7]
wrreq => scfifo_rl61:auto_generated.wrreq
rdreq => scfifo_rl61:auto_generated.rdreq
clock => scfifo_rl61:auto_generated.clock
aclr => scfifo_rl61:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_rl61:auto_generated.empty
full <= scfifo_rl61:auto_generated.full
almost_full <= scfifo_rl61:auto_generated.almost_full
almost_empty <= <GND>
usedw[0] <= scfifo_rl61:auto_generated.usedw[0]
usedw[1] <= scfifo_rl61:auto_generated.usedw[1]
usedw[2] <= scfifo_rl61:auto_generated.usedw[2]
usedw[3] <= scfifo_rl61:auto_generated.usedw[3]
usedw[4] <= scfifo_rl61:auto_generated.usedw[4]
usedw[5] <= scfifo_rl61:auto_generated.usedw[5]
usedw[6] <= scfifo_rl61:auto_generated.usedw[6]
usedw[7] <= scfifo_rl61:auto_generated.usedw[7]
usedw[8] <= scfifo_rl61:auto_generated.usedw[8]


|CPCI_exp|_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated
aclr => a_dpfifo_8l31:dpfifo.aclr
almost_full <= dffe_af.DB_MAX_OUTPUT_PORT_TYPE
clock => a_dpfifo_8l31:dpfifo.clock
clock => dffe_af.CLK
data[0] => a_dpfifo_8l31:dpfifo.data[0]
data[1] => a_dpfifo_8l31:dpfifo.data[1]
data[2] => a_dpfifo_8l31:dpfifo.data[2]
data[3] => a_dpfifo_8l31:dpfifo.data[3]
data[4] => a_dpfifo_8l31:dpfifo.data[4]
data[5] => a_dpfifo_8l31:dpfifo.data[5]
data[6] => a_dpfifo_8l31:dpfifo.data[6]
data[7] => a_dpfifo_8l31:dpfifo.data[7]
empty <= a_dpfifo_8l31:dpfifo.empty
full <= a_dpfifo_8l31:dpfifo.full
q[0] <= a_dpfifo_8l31:dpfifo.q[0]
q[1] <= a_dpfifo_8l31:dpfifo.q[1]
q[2] <= a_dpfifo_8l31:dpfifo.q[2]
q[3] <= a_dpfifo_8l31:dpfifo.q[3]
q[4] <= a_dpfifo_8l31:dpfifo.q[4]
q[5] <= a_dpfifo_8l31:dpfifo.q[5]
q[6] <= a_dpfifo_8l31:dpfifo.q[6]
q[7] <= a_dpfifo_8l31:dpfifo.q[7]
rdreq => a_dpfifo_8l31:dpfifo.rreq
usedw[0] <= a_dpfifo_8l31:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_8l31:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_8l31:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_8l31:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_8l31:dpfifo.usedw[4]
usedw[5] <= a_dpfifo_8l31:dpfifo.usedw[5]
usedw[6] <= a_dpfifo_8l31:dpfifo.usedw[6]
usedw[7] <= a_dpfifo_8l31:dpfifo.usedw[7]
usedw[8] <= a_dpfifo_8l31:dpfifo.usedw[8]
wrreq => a_dpfifo_8l31:dpfifo.wreq


|CPCI_exp|_422_to_fifo1:inst8|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo
aclr => cntr_vbb:rd_ptr_msb.aclr
aclr => cntr_cc7:usedw_counter.aclr
aclr => cntr_0cb:wr_ptr.aclr
clock => altsyncram_boa1:FIFOram.clock0
clock => altsyncram_boa1:FIFOram.clock1
clock => cntr_vbb:rd_ptr_msb.clock