prev_cmp_ad_test.tan.qmsg

多功能卡的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clock register bit_counter\[2\] register dout\[4\]~reg0 292.65 MHz 3.417 ns Internal " "Info: Clock \"sys_clock\" has Internal fmax of 292.65 MHz between source register \"bit_counter\[2\]\" and destination register \"dout\[4\]~reg0\" (period= 3.417 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.186 ns + Longest register register " "Info: + Longest register to register delay is 3.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bit_counter\[2\] 1 REG LC_X20_Y11_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N6; Fanout = 3; REG Node = 'bit_counter\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { bit_counter[2] } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.522 ns) 0.987 ns always2~25 2 COMB LC_X20_Y11_N1 2 " "Info: 2: + IC(0.465 ns) + CELL(0.522 ns) = 0.987 ns; Loc. = LC_X20_Y11_N1; Fanout = 2; COMB Node = 'always2~25'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.987 ns" { bit_counter[2] always2~25 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.101 ns) 1.249 ns dout\[0\]~92 3 COMB LC_X20_Y11_N2 8 " "Info: 3: + IC(0.161 ns) + CELL(0.101 ns) = 1.249 ns; Loc. = LC_X20_Y11_N2; Fanout = 8; COMB Node = 'dout\[0\]~92'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.262 ns" { always2~25 dout[0]~92 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.767 ns) 3.186 ns dout\[4\]~reg0 4 REG LC_X20_Y10_N3 1 " "Info: 4: + IC(1.170 ns) + CELL(0.767 ns) = 3.186 ns; Loc. = LC_X20_Y10_N3; Fanout = 1; REG Node = 'dout\[4\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.937 ns" { dout[0]~92 dout[4]~reg0 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.390 ns ( 43.63 % ) " "Info: Total cell delay = 1.390 ns ( 43.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.796 ns ( 56.37 % ) " "Info: Total interconnect delay = 1.796 ns ( 56.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.186 ns" { bit_counter[2] always2~25 dout[0]~92 dout[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.186 ns" { bit_counter[2] {} always2~25 {} dout[0]~92 {} dout[4]~reg0 {} } { 0.000ns 0.465ns 0.161ns 1.170ns } { 0.000ns 0.522ns 0.101ns 0.767ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 2.602 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clock\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sys_clock 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'sys_clock'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.629 ns) 2.602 ns dout\[4\]~reg0 2 REG LC_X20_Y10_N3 1 " "Info: 2: + IC(0.674 ns) + CELL(0.629 ns) = 2.602 ns; Loc. = LC_X20_Y10_N3; Fanout = 1; REG Node = 'dout\[4\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { sys_clock dout[4]~reg0 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.10 % ) " "Info: Total cell delay = 1.928 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.674 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock dout[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} dout[4]~reg0 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 2.602 ns - Longest register " "Info: - Longest clock path from clock \"sys_clock\" to source register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sys_clock 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'sys_clock'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.629 ns) 2.602 ns bit_counter\[2\] 2 REG LC_X20_Y11_N6 3 " "Info: 2: + IC(0.674 ns) + CELL(0.629 ns) = 2.602 ns; Loc. = LC_X20_Y11_N6; Fanout = 3; REG Node = 'bit_counter\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { sys_clock bit_counter[2] } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.10 % ) " "Info: Total cell delay = 1.928 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.674 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock bit_counter[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} bit_counter[2] {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock dout[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} dout[4]~reg0 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock bit_counter[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} bit_counter[2] {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.186 ns" { bit_counter[2] always2~25 dout[0]~92 dout[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.186 ns" { bit_counter[2] {} always2~25 {} dout[0]~92 {} dout[4]~reg0 {} } { 0.000ns 0.465ns 0.161ns 1.170ns } { 0.000ns 0.522ns 0.101ns 0.767ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock dout[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} dout[4]~reg0 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock bit_counter[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} bit_counter[2] {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data\[2\] r_enable sys_clock 7.079 ns register " "Info: tsu for register \"data\[2\]\" (data pin = \"r_enable\", clock pin = \"sys_clock\") is 7.079 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.648 ns + Longest pin register " "Info: + Longest pin to register delay is 9.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns r_enable 1 PIN PIN_21 13 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_21; Fanout = 13; PIN Node = 'r_enable'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_enable } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.067 ns) + CELL(0.390 ns) 7.756 ns data\[0\]~192 2 COMB LC_X21_Y11_N5 8 " "Info: 2: + IC(6.067 ns) + CELL(0.390 ns) = 7.756 ns; Loc. = LC_X21_Y11_N5; Fanout = 8; COMB Node = 'data\[0\]~192'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.457 ns" { r_enable data[0]~192 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.767 ns) 9.648 ns data\[2\] 3 REG LC_X20_Y10_N6 2 " "Info: 3: + IC(1.125 ns) + CELL(0.767 ns) = 9.648 ns; Loc. = LC_X20_Y10_N6; Fanout = 2; REG Node = 'data\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.892 ns" { data[0]~192 data[2] } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.456 ns ( 25.46 % ) " "Info: Total cell delay = 2.456 ns ( 25.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.192 ns ( 74.54 % ) " "Info: Total interconnect delay = 7.192 ns ( 74.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.648 ns" { r_enable data[0]~192 data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.648 ns" { r_enable {} r_enable~out0 {} data[0]~192 {} data[2] {} } { 0.000ns 0.000ns 6.067ns 1.125ns } { 0.000ns 1.299ns 0.390ns 0.767ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 2.602 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clock\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sys_clock 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'sys_clock'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.629 ns) 2.602 ns data\[2\] 2 REG LC_X20_Y10_N6 2 " "Info: 2: + IC(0.674 ns) + CELL(0.629 ns) = 2.602 ns; Loc. = LC_X20_Y10_N6; Fanout = 2; REG Node = 'data\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { sys_clock data[2] } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.10 % ) " "Info: Total cell delay = 1.928 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.674 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} data[2] {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.648 ns" { r_enable data[0]~192 data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.648 ns" { r_enable {} r_enable~out0 {} data[0]~192 {} data[2] {} } { 0.000ns 0.000ns 6.067ns 1.125ns } { 0.000ns 1.299ns 0.390ns 0.767ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock data[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} data[2] {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clock dout\[6\] dout\[6\]~reg0 7.598 ns register " "Info: tco from clock \"sys_clock\" to destination pin \"dout\[6\]\" through register \"dout\[6\]~reg0\" is 7.598 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 2.602 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to source register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sys_clock 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'sys_clock'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.629 ns) 2.602 ns dout\[6\]~reg0 2 REG LC_X20_Y10_N2 1 " "Info: 2: + IC(0.674 ns) + CELL(0.629 ns) = 2.602 ns; Loc. = LC_X20_Y10_N2; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { sys_clock dout[6]~reg0 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.10 % ) " "Info: Total cell delay = 1.928 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.674 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock dout[6]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} dout[6]~reg0 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.798 ns + Longest register pin " "Info: + Longest register to pin delay is 4.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[6\]~reg0 1 REG LC_X20_Y10_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N2; Fanout = 1; REG Node = 'dout\[6\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[6]~reg0 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.919 ns) + CELL(1.879 ns) 4.798 ns dout\[6\] 2 PIN PIN_41 0 " "Info: 2: + IC(2.919 ns) + CELL(1.879 ns) = 4.798 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dout\[6\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.798 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns ( 39.16 % ) " "Info: Total cell delay = 1.879 ns ( 39.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.919 ns ( 60.84 % ) " "Info: Total interconnect delay = 2.919 ns ( 60.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.798 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.798 ns" { dout[6]~reg0 {} dout[6] {} } { 0.000ns 2.919ns } { 0.000ns 1.879ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock dout[6]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} dout[6]~reg0 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.798 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.798 ns" { dout[6]~reg0 {} dout[6] {} } { 0.000ns 2.919ns } { 0.000ns 1.879ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sclk_reg1 sclk sys_clock -5.130 ns register " "Info: th for register \"sclk_reg1\" (data pin = \"sclk\", clock pin = \"sys_clock\") is -5.130 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 2.602 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to destination register is 2.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sys_clock 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'sys_clock'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clock } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.629 ns) 2.602 ns sclk_reg1 2 REG LC_X21_Y11_N5 5 " "Info: 2: + IC(0.674 ns) + CELL(0.629 ns) = 2.602 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; REG Node = 'sclk_reg1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { sys_clock sclk_reg1 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.10 % ) " "Info: Total cell delay = 1.928 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.674 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.674 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock sclk_reg1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} sclk_reg1 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.745 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns sclk 1 PIN PIN_38 1 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_38; Fanout = 1; PIN Node = 'sclk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.344 ns) + CELL(0.102 ns) 7.745 ns sclk_reg1 2 REG LC_X21_Y11_N5 5 " "Info: 2: + IC(6.344 ns) + CELL(0.102 ns) = 7.745 ns; Loc. = LC_X21_Y11_N5; Fanout = 5; REG Node = 'sclk_reg1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.446 ns" { sclk sclk_reg1 } "NODE_NAME" } } { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.401 ns ( 18.09 % ) " "Info: Total cell delay = 1.401 ns ( 18.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.344 ns ( 81.91 % ) " "Info: Total interconnect delay = 6.344 ns ( 81.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.745 ns" { sclk sclk_reg1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.745 ns" { sclk {} sclk~out0 {} sclk_reg1 {} } { 0.000ns 0.000ns 6.344ns } { 0.000ns 1.299ns 0.102ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.602 ns" { sys_clock sclk_reg1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.602 ns" { sys_clock {} sys_clock~out0 {} sclk_reg1 {} } { 0.000ns 0.000ns 0.674ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.745 ns" { sclk sclk_reg1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.745 ns" { sclk {} sclk~out0 {} sclk_reg1 {} } { 0.000ns 0.000ns 6.344ns } { 0.000ns 1.299ns 0.102ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}