📄 mux_1hc.tdf
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--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=8 LPM_WIDTH=16 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 8.0 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 VERSION_END
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 80
SUBDESIGN mux_1hc
(
data[127..0] : input;
result[15..0] : output;
sel[2..0] : input;
)
VARIABLE
result_node[15..0] : WIRE;
sel_ffs_wire[2..0] : WIRE;
sel_node[2..0] : WIRE;
w_data1000w[3..0] : WIRE;
w_data102w[3..0] : WIRE;
w_data103w[3..0] : WIRE;
w_data1046w[7..0] : WIRE;
w_data1068w[3..0] : WIRE;
w_data1069w[3..0] : WIRE;
w_data149w[7..0] : WIRE;
w_data171w[3..0] : WIRE;
w_data172w[3..0] : WIRE;
w_data218w[7..0] : WIRE;
w_data240w[3..0] : WIRE;
w_data241w[3..0] : WIRE;
w_data287w[7..0] : WIRE;
w_data309w[3..0] : WIRE;
w_data310w[3..0] : WIRE;
w_data31w[3..0] : WIRE;
w_data32w[3..0] : WIRE;
w_data356w[7..0] : WIRE;
w_data378w[3..0] : WIRE;
w_data379w[3..0] : WIRE;
w_data425w[7..0] : WIRE;
w_data447w[3..0] : WIRE;
w_data448w[3..0] : WIRE;
w_data494w[7..0] : WIRE;
w_data516w[3..0] : WIRE;
w_data517w[3..0] : WIRE;
w_data563w[7..0] : WIRE;
w_data585w[3..0] : WIRE;
w_data586w[3..0] : WIRE;
w_data632w[7..0] : WIRE;
w_data654w[3..0] : WIRE;
w_data655w[3..0] : WIRE;
w_data701w[7..0] : WIRE;
w_data723w[3..0] : WIRE;
w_data724w[3..0] : WIRE;
w_data770w[7..0] : WIRE;
w_data792w[3..0] : WIRE;
w_data793w[3..0] : WIRE;
w_data80w[7..0] : WIRE;
w_data839w[7..0] : WIRE;
w_data861w[3..0] : WIRE;
w_data862w[3..0] : WIRE;
w_data908w[7..0] : WIRE;
w_data930w[3..0] : WIRE;
w_data931w[3..0] : WIRE;
w_data977w[7..0] : WIRE;
w_data999w[3..0] : WIRE;
w_data9w[7..0] : WIRE;
w_sel1001w[1..0] : WIRE;
w_sel104w[1..0] : WIRE;
w_sel1070w[1..0] : WIRE;
w_sel173w[1..0] : WIRE;
w_sel242w[1..0] : WIRE;
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