dcfifo_cph1.tdf

多功能卡的源代码

--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=11 LPM_WIDTHU_R=11 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq wrclk wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 8.0 cbx_a_gray2bin 2008:02:23:252825 cbx_a_graycounter 2008:02:23:252825 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_dcfifo 2008:04:22:277785 cbx_fifo_common 2008:02:23:252825 cbx_flex10ke 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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FUNCTION a_gray2bin_36b (gray[10..0])
RETURNS ( bin[10..0]);
FUNCTION a_graycounter_826 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION a_graycounter_2r6 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION altsyncram_3vq (address_a[10..0], address_b[10..0], clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION alt_synch_pipe_vd8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION dffpipe_pe9 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION alt_synch_pipe_0e8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION add_sub_pvb (dataa[10..0], datab[10..0])
RETURNS ( result[10..0]);

--synthesis_resources = lut 70 M4K 8 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;{ -from ""rdptr_g|power_modified_counter_values"" -to ""ws_dgrp|dffpipe10|dffe11a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *rdptr_g|power_modified_counter_values* -to *ws_dgrp|dffpipe_te9:dffpipe10|dffe11a* "";{ -from ""delayed_wrptr_g"" -to ""rs_dgwp|dffpipe8|dffe9a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe8|dffe9a* """;

SUBDESIGN dcfifo_cph1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[10..0]	:	output;
) 
VARIABLE 
	wrptr_g_gray2bin : a_gray2bin_36b;
	ws_dgrp_gray2bin : a_gray2bin_36b;
	rdptr_g : a_graycounter_826;
	rdptr_g1p : a_graycounter_2r6;
	wrptr_g1p : a_graycounter_2r6;
	fifo_ram : altsyncram_3vq;
	delayed_wrptr_g[10..0] : dffe;
	wrptr_g[10..0] : dffe;
	rs_dgwp : alt_synch_pipe_vd8;
	ws_brp : dffpipe_pe9;
	ws_bwp : dffpipe_pe9;
	ws_dgrp : alt_synch_pipe_0e8;
	wrusedw_sub : add_sub_pvb;
	rdempty_eq_comp_aeb_int	:	WIRE;
	rdempty_eq_comp_aeb	:	WIRE;
	rdempty_eq_comp_dataa[10..0]	:	WIRE;
	rdempty_eq_comp_datab[10..0]	:	WIRE;
	wrfull_eq_comp_aeb_int	:	WIRE;
	wrfull_eq_comp_aeb	:	WIRE;
	wrfull_eq_comp_dataa[10..0]	:	WIRE;
	wrfull_eq_comp_datab[10..0]	:	WIRE;
	dup_valid_wrreq	: WIRE;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;

BEGIN 
	wrptr_g_gray2bin.gray[] = wrptr_g[].q;
	ws_dgrp_gray2bin.gray[] = ws_dgrp.q[];
	rdptr_g.aclr = aclr;
	rdptr_g.clock = rdclk;
	rdptr_g.cnt_en = valid_rdreq;
	rdptr_g1p.aclr = aclr;
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = valid_rdreq;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = dup_valid_wrreq;
	fifo_ram.address_a[] = wrptr_g[].q;
	fifo_ram.address_b[] = ((rdptr_g.q[] & int_rdempty) # (rdptr_g1p.q[] & (! int_rdempty)));
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = (valid_rdreq # int_rdempty);
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].clrn = (! aclr);
	delayed_wrptr_g[].d = wrptr_g[].q;
	wrptr_g[].clk = wrclk;
	wrptr_g[].clrn = (! aclr);
	wrptr_g[].d = wrptr_g1p.q[];
	wrptr_g[].ena = valid_wrreq;
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_brp.clock = wrclk;
	ws_brp.clrn = (! aclr);
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.clrn = (! aclr);
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g.q[];
	wrusedw_sub.dataa[] = ws_bwp.q[];
	wrusedw_sub.datab[] = ws_brp.q[];
	IF (rdempty_eq_comp_dataa[] == rdempty_eq_comp_datab[]) THEN
		rdempty_eq_comp_aeb_int = VCC;
	ELSE
		rdempty_eq_comp_aeb_int = GND;
	END IF;
	rdempty_eq_comp_aeb = rdempty_eq_comp_aeb_int;
	rdempty_eq_comp_dataa[] = rs_dgwp.q[];
	rdempty_eq_comp_datab[] = rdptr_g.q[];
	IF (wrfull_eq_comp_dataa[] == wrfull_eq_comp_datab[]) THEN
		wrfull_eq_comp_aeb_int = VCC;
	ELSE
		wrfull_eq_comp_aeb_int = GND;
	END IF;
	wrfull_eq_comp_aeb = wrfull_eq_comp_aeb_int;
	wrfull_eq_comp_dataa[] = ws_dgrp.q[];
	wrfull_eq_comp_datab[] = wrptr_g1p.q[];
	dup_valid_wrreq = (wrreq & (! int_wrfull));
	int_rdempty = rdempty_eq_comp_aeb;
	int_wrfull = wrfull_eq_comp_aeb;
	q[] = fifo_ram.q_b[];
	rdempty = int_rdempty;
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrfull = int_wrfull;
	wrusedw[] = wrusedw_sub.result[];
END;
--VALID FILE