ad_test.tan.qmsg

多功能卡的源代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK register _232_to_fifo:inst5\|inst4 register _232_to_fifo:inst5\|inst3 6.687 ns " "Info: Slack time is 6.687 ns for clock \"CLK\" between source register \"_232_to_fifo:inst5\|inst4\" and destination register \"_232_to_fifo:inst5\|inst3\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "59.07 MHz 16.928 ns " "Info: Fmax is 59.07 MHz (period= 16.928 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "8.929 ns + Largest register register " "Info: + Largest register to register requirement is 8.929 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "15.151 ns + " "Info: + Setup relationship between source and destination is 15.151 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 15.151 ns " "Info: + Latch edge is 15.151 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK 30.303 ns 15.151 ns inverted 50 " "Info: Clock period of Destination clock \"CLK\" is 30.303 ns with inverted offset of 15.151 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK 30.303 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK\" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.991 ns + Largest " "Info: + Largest clock skew is -5.991 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.573 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns CLK 1 CLK PIN_28 98 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 98; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { -352 328 496 -336 "CLK" "" } { 592 -616 -544 608 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(0.629 ns) 2.573 ns _232_to_fifo:inst5\|inst3 2 REG LC_X23_Y9_N9 33 " "Info: 2: + IC(0.645 ns) + CELL(0.629 ns) = 2.573 ns; Loc. = LC_X23_Y9_N9; Fanout = 33; REG Node = '_232_to_fifo:inst5\|inst3'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { CLK _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 680 744 488 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 74.93 % ) " "Info: Total cell delay = 1.928 ns ( 74.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.645 ns ( 25.07 % ) " "Info: Total interconnect delay = 0.645 ns ( 25.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { CLK _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 0.000ns 0.645ns } { 0.000ns 1.299ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.564 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 8.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns CLK 1 CLK PIN_28 98 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 98; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { -352 328 496 -336 "CLK" "" } { 592 -616 -544 608 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.827 ns) 2.800 ns _232_to_fifo:inst5\|clk_txd:inst1\|clk16x_mid\[0\] 2 REG LC_X27_Y10_N9 3 " "Info: 2: + IC(0.674 ns) + CELL(0.827 ns) = 2.800 ns; Loc. = LC_X27_Y10_N9; Fanout = 3; REG Node = '_232_to_fifo:inst5\|clk_txd:inst1\|clk16x_mid\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { CLK _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] } "NODE_NAME" } } { "clk_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_txd.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.497 ns) + CELL(0.258 ns) 3.555 ns _232_to_fifo:inst5\|clk_txd:inst1\|clk16x 3 COMB LC_X27_Y10_N7 38 " "Info: 3: + IC(0.497 ns) + CELL(0.258 ns) = 3.555 ns; Loc. = LC_X27_Y10_N7; Fanout = 38; COMB Node = '_232_to_fifo:inst5\|clk_txd:inst1\|clk16x'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] _232_to_fifo:inst5|clk_txd:inst1|clk16x } "NODE_NAME" } } { "clk_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_txd.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.050 ns) + CELL(0.827 ns) 7.432 ns _232_to_fifo:inst5\|lt_uart_r5:inst6\|wrn 4 REG LC_X10_Y10_N4 2 " "Info: 4: + IC(3.050 ns) + CELL(0.827 ns) = 7.432 ns; Loc. = LC_X10_Y10_N4; Fanout = 2; REG Node = '_232_to_fifo:inst5\|lt_uart_r5:inst6\|wrn'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.877 ns" { _232_to_fifo:inst5|clk_txd:inst1|clk16x _232_to_fifo:inst5|lt_uart_r5:inst6|wrn } "NODE_NAME" } } { "lt_uart_r5.v" "" { Text "C:/Users/liutong/Desktop/CPCI/lt_uart_r5.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.503 ns) + CELL(0.629 ns) 8.564 ns _232_to_fifo:inst5\|inst4 5 REG LC_X10_Y10_N8 1 " "Info: 5: + IC(0.503 ns) + CELL(0.629 ns) = 8.564 ns; Loc. = LC_X10_Y10_N8; Fanout = 1; REG Node = '_232_to_fifo:inst5\|inst4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { _232_to_fifo:inst5|lt_uart_r5:inst6|wrn _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 536 600 488 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.840 ns ( 44.84 % ) " "Info: Total cell delay = 3.840 ns ( 44.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.724 ns ( 55.16 % ) " "Info: Total interconnect delay = 4.724 ns ( 55.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { CLK _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] _232_to_fifo:inst5|clk_txd:inst1|clk16x _232_to_fifo:inst5|lt_uart_r5:inst6|wrn _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] {} _232_to_fifo:inst5|clk_txd:inst1|clk16x {} _232_to_fifo:inst5|lt_uart_r5:inst6|wrn {} _232_to_fifo:inst5|inst4 {} } { 0.000ns 0.000ns 0.674ns 0.497ns 3.050ns 0.503ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { CLK _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 0.000ns 0.645ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { CLK _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] _232_to_fifo:inst5|clk_txd:inst1|clk16x _232_to_fifo:inst5|lt_uart_r5:inst6|wrn _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] {} _232_to_fifo:inst5|clk_txd:inst1|clk16x {} _232_to_fifo:inst5|lt_uart_r5:inst6|wrn {} _232_to_fifo:inst5|inst4 {} } { 0.000ns 0.000ns 0.674ns 0.497ns 3.050ns 0.503ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 536 600 488 "inst4" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns - " "Info: - Micro setup delay of destination is 0.033 ns" {  } { { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 680 744 488 "inst3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { CLK _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 0.000ns 0.645ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { CLK _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] _232_to_fifo:inst5|clk_txd:inst1|clk16x _232_to_fifo:inst5|lt_uart_r5:inst6|wrn _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] {} _232_to_fifo:inst5|clk_txd:inst1|clk16x {} _232_to_fifo:inst5|lt_uart_r5:inst6|wrn {} _232_to_fifo:inst5|inst4 {} } { 0.000ns 0.000ns 0.674ns 0.497ns 3.050ns 0.503ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.242 ns - Longest register register " "Info: - Longest register to register delay is 2.242 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _232_to_fifo:inst5\|inst4 1 REG LC_X10_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N8; Fanout = 1; REG Node = '_232_to_fifo:inst5\|inst4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 536 600 488 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.140 ns) + CELL(0.102 ns) 2.242 ns _232_to_fifo:inst5\|inst3 2 REG LC_X23_Y9_N9 33 " "Info: 2: + IC(2.140 ns) + CELL(0.102 ns) = 2.242 ns; Loc. = LC_X23_Y9_N9; Fanout = 33; REG Node = '_232_to_fifo:inst5\|inst3'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.242 ns" { _232_to_fifo:inst5|inst4 _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "_232_to_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_232_to_fifo.bdf" { { 408 680 744 488 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.102 ns ( 4.55 % ) " "Info: Total cell delay = 0.102 ns ( 4.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.140 ns ( 95.45 % ) " "Info: Total interconnect delay = 2.140 ns ( 95.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.242 ns" { _232_to_fifo:inst5|inst4 _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.242 ns" { _232_to_fifo:inst5|inst4 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 2.140ns } { 0.000ns 0.102ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { CLK _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 0.000ns 0.645ns } { 0.000ns 1.299ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.564 ns" { CLK _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] _232_to_fifo:inst5|clk_txd:inst1|clk16x _232_to_fifo:inst5|lt_uart_r5:inst6|wrn _232_to_fifo:inst5|inst4 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.564 ns" { CLK {} CLK~out0 {} _232_to_fifo:inst5|clk_txd:inst1|clk16x_mid[0] {} _232_to_fifo:inst5|clk_txd:inst1|clk16x {} _232_to_fifo:inst5|lt_uart_r5:inst6|wrn {} _232_to_fifo:inst5|inst4 {} } { 0.000ns 0.000ns 0.674ns 0.497ns 3.050ns 0.503ns } { 0.000ns 1.299ns 0.827ns 0.258ns 0.827ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.242 ns" { _232_to_fifo:inst5|inst4 _232_to_fifo:inst5|inst3 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.242 ns" { _232_to_fifo:inst5|inst4 {} _232_to_fifo:inst5|inst3 {} } { 0.000ns 2.140ns } { 0.000ns 0.102ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 register _422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\] register _422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\] 727 ps " "Info: Minimum slack time is 727 ps for clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" between source register \"_422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\]\" and destination register \"_422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.542 ns + Shortest register register " "Info: + Shortest register to register delay is 0.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\] 1 REG LC_X15_Y14_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y14_N9; Fanout = 2; REG Node = '_422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] } "NODE_NAME" } } { "db/a_dpfifo_8l31.tdf" "" { Text "C:/Users/liutong/Desktop/CPCI/db/a_dpfifo_8l31.tdf" 47 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.542 ns) 0.542 ns _422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\] 2 REG LC_X15_Y14_N9 2 " "Info: 2: + IC(0.000 ns) + CELL(0.542 ns) = 0.542 ns; Loc. = LC_X15_Y14_N9; Fanout = 2; REG Node = '_422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.542 ns" { _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] } "NODE_NAME" } } { "db/a_dpfifo_8l31.tdf" "" { Text "C:/Users/liutong/Desktop/CPCI/db/a_dpfifo_8l31.tdf" 47 14 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns ( 100.00 % ) " "Info: Total cell delay = 0.542 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.542 ns" { _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.542 ns" { _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] {} _422_to_fifo3:inst21|_422_fifo:inst3|scfifo:scfifo_component|scfifo_rl61:auto_generated|a_dpfifo_8l31:dpfifo|low_addressa[8] {} } { 0.000ns 0.000ns } { 0.000ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.185 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.185 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.667 ns " "Info: + Latch edge is -1.667 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk0 15.151 ns -1.667 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 15.151 ns with  offset of -1.667 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.667 ns " "Info: - Launch edge is -1.667 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk0 15.151 ns -1.667 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 15.151 ns with  offset of -1.667 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 destination 2.120 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1215 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1215; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.491 ns) + CELL(0.629 ns) 2.120 ns _422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\] 2 REG LC_X15_Y14_N9 2 " "Info: 2: + IC(1.491 ns) + CELL(0.629 ns) = 2.120 ns; Loc. = LC_X15_Y14_N9; Fanout = 2; REG Node = '_422_to_fifo3:inst21\|_422_fifo:inst3\|scfifo:scfifo_component\|scfifo_rl61:auto_generated\|a_dpfifo_8l31:dpfifo\|low_addressa\[8\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.120 ns" { altpll0:inst|altpll:altpll_compone