ad_test.tan.qmsg

多功能卡的源代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 register dma:inst6\|currentstate.s5 register core1:inst23\|read_bkfifo_counter\[1\] 1.489 ns " "Info: Slack time is 1.489 ns for clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" between source register \"dma:inst6\|currentstate.s5\" and destination register \"core1:inst23\|read_bkfifo_counter\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.344 ns + Largest register register " "Info: + Largest register to register requirement is 7.344 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.575 ns + " "Info: + Setup relationship between source and destination is 7.575 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 21.059 ns " "Info: + Latch edge is 21.059 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk0 15.151 ns 5.908 ns inverted 50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" is 15.151 ns with inverted offset of 5.908 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 13.484 ns " "Info: - Launch edge is 13.484 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk1 30.303 ns -1.667 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" is 30.303 ns with  offset of -1.667 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk0 destination 2.080 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1215 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1215; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.629 ns) 2.080 ns core1:inst23\|read_bkfifo_counter\[1\] 2 REG LC_X25_Y4_N7 3 " "Info: 2: + IC(1.451 ns) + CELL(0.629 ns) = 2.080 ns; Loc. = LC_X25_Y4_N7; Fanout = 3; REG Node = 'core1:inst23\|read_bkfifo_counter\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 546 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns ( 30.24 % ) " "Info: Total cell delay = 0.629 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 69.76 % ) " "Info: Total interconnect delay = 1.451 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk1 source 2.080 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" to source register is 2.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 8; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.629 ns) 2.080 ns dma:inst6\|currentstate.s5 2 REG LC_X24_Y8_N0 3 " "Info: 2: + IC(1.451 ns) + CELL(0.629 ns) = 2.080 ns; Loc. = LC_X24_Y8_N0; Fanout = 3; REG Node = 'dma:inst6\|currentstate.s5'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s5 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns ( 30.24 % ) " "Info: Total cell delay = 0.629 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 69.76 % ) " "Info: Total interconnect delay = 1.451 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s5 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s5 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s5 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s5 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns - " "Info: - Micro setup delay of destination is 0.033 ns" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 546 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s5 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s5 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.855 ns - Longest register register " "Info: - Longest register to register delay is 5.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dma:inst6\|currentstate.s5 1 REG LC_X24_Y8_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y8_N0; Fanout = 3; REG Node = 'dma:inst6\|currentstate.s5'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dma:inst6|currentstate.s5 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.469 ns) + CELL(0.390 ns) 0.859 ns dma:inst6\|WideOr2~14 2 COMB LC_X24_Y8_N6 3 " "Info: 2: + IC(0.469 ns) + CELL(0.390 ns) = 0.859 ns; Loc. = LC_X24_Y8_N6; Fanout = 3; COMB Node = 'dma:inst6\|WideOr2~14'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.859 ns" { dma:inst6|currentstate.s5 dma:inst6|WideOr2~14 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 166 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.101 ns) 1.329 ns dma:inst6\|read_bkfifo_request~56 3 COMB LC_X24_Y8_N1 5 " "Info: 3: + IC(0.369 ns) + CELL(0.101 ns) = 1.329 ns; Loc. = LC_X24_Y8_N1; Fanout = 5; COMB Node = 'dma:inst6\|read_bkfifo_request~56'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.470 ns" { dma:inst6|WideOr2~14 dma:inst6|read_bkfifo_request~56 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.258 ns) 2.240 ns dma:inst6\|read_bkfifo_start~167 4 COMB LC_X24_Y8_N3 21 " "Info: 4: + IC(0.653 ns) + CELL(0.258 ns) = 2.240 ns; Loc. = LC_X24_Y8_N3; Fanout = 21; COMB Node = 'dma:inst6\|read_bkfifo_start~167'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { dma:inst6|read_bkfifo_request~56 dma:inst6|read_bkfifo_start~167 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.522 ns) 3.964 ns core1:inst23\|read_bkfifo_counter\[1\]~842 5 COMB LC_X25_Y5_N3 12 " "Info: 5: + IC(1.202 ns) + CELL(0.522 ns) = 3.964 ns; Loc. = LC_X25_Y5_N3; Fanout = 12; COMB Node = 'core1:inst23\|read_bkfifo_counter\[1\]~842'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.724 ns" { dma:inst6|read_bkfifo_start~167 core1:inst23|read_bkfifo_counter[1]~842 } "NODE_NAME" } } { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 546 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.124 ns) + CELL(0.767 ns) 5.855 ns core1:inst23\|read_bkfifo_counter\[1\] 6 REG LC_X25_Y4_N7 3 " "Info: 6: + IC(1.124 ns) + CELL(0.767 ns) = 5.855 ns; Loc. = LC_X25_Y4_N7; Fanout = 3; REG Node = 'core1:inst23\|read_bkfifo_counter\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.891 ns" { core1:inst23|read_bkfifo_counter[1]~842 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 546 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.038 ns ( 34.81 % ) " "Info: Total cell delay = 2.038 ns ( 34.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.817 ns ( 65.19 % ) " "Info: Total interconnect delay = 3.817 ns ( 65.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.855 ns" { dma:inst6|currentstate.s5 dma:inst6|WideOr2~14 dma:inst6|read_bkfifo_request~56 dma:inst6|read_bkfifo_start~167 core1:inst23|read_bkfifo_counter[1]~842 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.855 ns" { dma:inst6|currentstate.s5 {} dma:inst6|WideOr2~14 {} dma:inst6|read_bkfifo_request~56 {} dma:inst6|read_bkfifo_start~167 {} core1:inst23|read_bkfifo_counter[1]~842 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 0.469ns 0.369ns 0.653ns 1.202ns 1.124ns } { 0.000ns 0.390ns 0.101ns 0.258ns 0.522ns 0.767ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk0 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s5 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s5 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.855 ns" { dma:inst6|currentstate.s5 dma:inst6|WideOr2~14 dma:inst6|read_bkfifo_request~56 dma:inst6|read_bkfifo_start~167 core1:inst23|read_bkfifo_counter[1]~842 core1:inst23|read_bkfifo_counter[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.855 ns" { dma:inst6|currentstate.s5 {} dma:inst6|WideOr2~14 {} dma:inst6|read_bkfifo_request~56 {} dma:inst6|read_bkfifo_start~167 {} core1:inst23|read_bkfifo_counter[1]~842 {} core1:inst23|read_bkfifo_counter[1] {} } { 0.000ns 0.469ns 0.369ns 0.653ns 1.202ns 1.124ns } { 0.000ns 0.390ns 0.101ns 0.258ns 0.522ns 0.767ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk1 register dma:inst6\|currentstate.s6 register dma:inst6\|currentstate.s1 28.701 ns " "Info: Slack time is 28.701 ns for clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" between source register \"dma:inst6\|currentstate.s6\" and destination register \"dma:inst6\|currentstate.s1\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "320.1 MHz " "Info: Fmax is restricted to 320.1 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "30.072 ns + Largest register register " "Info: + Largest register to register requirement is 30.072 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "30.303 ns + " "Info: + Setup relationship between source and destination is 30.303 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 28.636 ns " "Info: + Latch edge is 28.636 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst\|altpll:altpll_component\|_clk1 30.303 ns -1.667 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" is 30.303 ns with  offset of -1.667 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.667 ns " "Info: - Launch edge is -1.667 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst\|altpll:altpll_component\|_clk1 30.303 ns -1.667 ns  50 " "Info: Clock period of Source clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" is 30.303 ns with  offset of -1.667 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk1 destination 2.080 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" to destination register is 2.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 8; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.629 ns) 2.080 ns dma:inst6\|currentstate.s1 2 REG LC_X24_Y8_N9 2 " "Info: 2: + IC(1.451 ns) + CELL(0.629 ns) = 2.080 ns; Loc. = LC_X24_Y8_N9; Fanout = 2; REG Node = 'dma:inst6\|currentstate.s1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns ( 30.24 % ) " "Info: Total cell delay = 0.629 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 69.76 % ) " "Info: Total interconnect delay = 1.451 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s1 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst\|altpll:altpll_component\|_clk1 source 2.080 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst\|altpll:altpll_component\|_clk1\" to source register is 2.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 8; CLK Node = 'altpll0:inst\|altpll:altpll_component\|_clk1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/80/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.629 ns) 2.080 ns dma:inst6\|currentstate.s6 2 REG LC_X24_Y8_N5 2 " "Info: 2: + IC(1.451 ns) + CELL(0.629 ns) = 2.080 ns; Loc. = LC_X24_Y8_N5; Fanout = 2; REG Node = 'dma:inst6\|currentstate.s6'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s6 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.629 ns ( 30.24 % ) " "Info: Total cell delay = 0.629 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 69.76 % ) " "Info: Total interconnect delay = 1.451 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s6 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s6 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s1 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s6 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s6 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns - " "Info: - Micro clock to output delay of source is 0.198 ns" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns - " "Info: - Micro setup delay of destination is 0.033 ns" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s1 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s6 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s6 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.371 ns - Longest register register " "Info: - Longest register to register delay is 1.371 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dma:inst6\|currentstate.s6 1 REG LC_X24_Y8_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y8_N5; Fanout = 2; REG Node = 'dma:inst6\|currentstate.s6'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dma:inst6|currentstate.s6 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.653 ns) 1.371 ns dma:inst6\|currentstate.s1 2 REG LC_X24_Y8_N9 2 " "Info: 2: + IC(0.718 ns) + CELL(0.653 ns) = 1.371 ns; Loc. = LC_X24_Y8_N9; Fanout = 2; REG Node = 'dma:inst6\|currentstate.s1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { dma:inst6|currentstate.s6 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.653 ns ( 47.63 % ) " "Info: Total cell delay = 0.653 ns ( 47.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.718 ns ( 52.37 % ) " "Info: Total interconnect delay = 0.718 ns ( 52.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { dma:inst6|currentstate.s6 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.371 ns" { dma:inst6|currentstate.s6 {} dma:inst6|currentstate.s1 {} } { 0.000ns 0.718ns } { 0.000ns 0.653ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s1 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 dma:inst6|currentstate.s6 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.080 ns" { altpll0:inst|altpll:altpll_component|_clk1 {} dma:inst6|currentstate.s6 {} } { 0.000ns 1.451ns } { 0.000ns 0.629ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { dma:inst6|currentstate.s6 dma:inst6|currentstate.s1 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.371 ns" { dma:inst6|currentstate.s6 {} dma:inst6|currentstate.s1 {} } { 0.000ns 0.718ns } { 0.000ns 0.653ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}