dcfifo_2oi1.tdf

多功能卡的源代码

--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="ON" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=11 LPM_WIDTHU_R=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="OFF" aclr data q rdclk rdempty rdreq wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 8.0 cbx_a_gray2bin 2008:02:23:252825 cbx_a_graycounter 2008:02:23:252825 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_dcfifo 2008:04:22:277785 cbx_fifo_common 2008:02:23:252825 cbx_flex10ke 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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FUNCTION a_fefifo_76d (aclr, clock, rreq, usedw_in[10..0])
RETURNS ( empty, full);
FUNCTION a_fefifo_c6d (aclr, clock, usedw_in[10..0], wreq)
RETURNS ( empty, full);
FUNCTION a_gray2bin_36b (gray[10..0])
RETURNS ( bin[10..0]);
FUNCTION a_graycounter_2r6 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION a_graycounter_726 (aclr, clock, cnt_en)
RETURNS ( q[10..0]);
FUNCTION altdpram (aclr, byteena[WIDTH_BYTEENA-1..0], data[WIDTH-1..0], inclock, inclocken, outclock, outclocken, rdaddress[WIDTHAD-1..0], rdaddressstall, rden, wraddress[WIDTHAD-1..0], wraddressstall, wren)
WITH ( BYTE_SIZE, INDATA_ACLR, INDATA_REG, LPM_FILE, lpm_hint, MAXIMUM_DEPTH, NUMWORDS, OUTDATA_ACLR, OUTDATA_REG, RAM_BLOCK_TYPE, RDADDRESS_ACLR, RDADDRESS_REG, RDCONTROL_ACLR, RDCONTROL_REG, READ_DURING_WRITE_MODE_MIXED_PORTS, USE_EAB, WIDTH, WIDTH_BYTEENA = 1, WIDTHAD, WRADDRESS_ACLR, WRADDRESS_REG, WRCONTROL_ACLR, WRCONTROL_REG)
RETURNS ( q[WIDTH-1..0]);
FUNCTION dffpipe_pe9 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION alt_synch_pipe_1e8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION alt_synch_pipe_2e8 (clock, clrn, d[10..0])
RETURNS ( q[10..0]);
FUNCTION add_sub_pvb (dataa[10..0], datab[10..0])
RETURNS ( result[10..0]);
FUNCTION cntr_lua (aclr, clock, cnt_en)
RETURNS ( q[10..0]);

--synthesis_resources = altdpram 1 lut 265 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;{-to rdptrrg} PRESERVE_REGISTER=ON;{ -from ""write_delay_cycle"" -to ""dffpipe_rs_dgwp|dffpipe10|dffe11a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *write_delay_cycle* -to *dffpipe_rs_dgwp|dffpipe_re9:dffpipe10|dffe11a* "";{ -from ""rdptrrg"" -to ""dffpipe_ws_dgrp|dffpipe14|dffe15a"" }CUT=ON;-name SDC_STATEMENT ""set_false_path -from *rdptrrg* -to *dffpipe_ws_dgrp|dffpipe_se9:dffpipe14|dffe15a* """;

SUBDESIGN dcfifo_2oi1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[10..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[10..0]	:	output;
) 
VARIABLE 
	read_state : a_fefifo_76d;
	write_state : a_fefifo_c6d;
	gray2bin_rs_nbwp : a_gray2bin_36b;
	gray2bin_ws_nbrp : a_gray2bin_36b;
	rdptr_g : a_graycounter_2r6;
	wrptr_g : a_graycounter_726;
	fiforam : altdpram
		WITH (
			OUTDATA_REG = "OUTCLOCK",
			RDCONTROL_ACLR = "OFF",
			RDCONTROL_REG = "UNREGISTERED",
			USE_EAB = "OFF",
			WIDTH = 16,
			WIDTHAD = 11
		);
	rdptrrg[10..0] : dffe;
	write_delay_cycle[10..0] : dffe;
	dffpipe_rdbuw : dffpipe_pe9;
	dffpipe_rdusedw : dffpipe_pe9;
	dffpipe_rs_dbwp : dffpipe_pe9;
	dffpipe_rs_dgwp : alt_synch_pipe_1e8;
	dffpipe_wr_dbuw : dffpipe_pe9;
	dffpipe_wrusedw : dffpipe_pe9;
	dffpipe_ws_dgrp : alt_synch_pipe_2e8;
	dffpipe_ws_nbrp : dffpipe_pe9;
	lpm_add_sub_rd_udwn : add_sub_pvb;
	lpm_add_sub_wr_udwn : add_sub_pvb;
	rdptr_b : cntr_lua;
	wrptr_b : cntr_lua;
	rd_dbuw[10..0]	: WIRE;
	rd_udwn[10..0]	: WIRE;
	rs_dbwp[10..0]	: WIRE;
	rs_dgwp[10..0]	: WIRE;
	rs_nbwp[10..0]	: WIRE;
	tmp_aclr	: WIRE;
	tmp_data[10..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wr_dbuw[10..0]	: WIRE;
	wr_udwn[10..0]	: WIRE;
	ws_dbrp[10..0]	: WIRE;
	ws_dgrp[10..0]	: WIRE;
	ws_nbrp[10..0]	: WIRE;

BEGIN 
	read_state.aclr = aclr;
	read_state.clock = rdclk;
	read_state.rreq = rdreq;
	read_state.usedw_in[] = rd_dbuw[];
	write_state.aclr = aclr;
	write_state.clock = wrclk;
	write_state.usedw_in[] = wr_dbuw[];
	write_state.wreq = wrreq;
	gray2bin_rs_nbwp.gray[] = rs_dgwp[];
	gray2bin_ws_nbrp.gray[] = ws_dgrp[];
	rdptr_g.aclr = aclr;
	rdptr_g.clock = rdclk;
	rdptr_g.cnt_en = valid_rreq;
	wrptr_g.aclr = aclr;
	wrptr_g.clock = wrclk;
	wrptr_g.cnt_en = valid_wreq;
	fiforam.aclr = aclr;
	fiforam.data[] = data[];
	fiforam.inclock = wrclk;
	fiforam.outclock = rdclk;
	fiforam.outclocken = valid_rreq;
	fiforam.rdaddress[] = rdptr_g.q[];
	fiforam.wraddress[] = wrptr_g.q[];
	fiforam.wren = valid_wreq;
	rdptrrg[].clk = rdclk;
	rdptrrg[].clrn = (! aclr);
	rdptrrg[].d = rdptr_g.q[];
	rdptrrg[].ena = valid_rreq;
	write_delay_cycle[].clk = wrclk;
	write_delay_cycle[].clrn = (! aclr);
	write_delay_cycle[].d = wrptr_g.q[];
	dffpipe_rdbuw.clock = rdclk;
	dffpipe_rdbuw.clrn = tmp_aclr;
	dffpipe_rdbuw.d[] = rd_udwn[];
	dffpipe_rdusedw.clock = rdclk;
	dffpipe_rdusedw.clrn = tmp_aclr;
	dffpipe_rdusedw.d[] = rd_udwn[];
	dffpipe_rs_dbwp.clock = rdclk;
	dffpipe_rs_dbwp.clrn = tmp_aclr;
	dffpipe_rs_dbwp.d[] = rs_nbwp[];
	dffpipe_rs_dgwp.clock = rdclk;
	dffpipe_rs_dgwp.clrn = tmp_aclr;
	dffpipe_rs_dgwp.d[] = write_delay_cycle[].q;
	dffpipe_wr_dbuw.clock = wrclk;
	dffpipe_wr_dbuw.clrn = tmp_aclr;
	dffpipe_wr_dbuw.d[] = wr_udwn[];
	dffpipe_wrusedw.clock = wrclk;
	dffpipe_wrusedw.clrn = tmp_aclr;
	dffpipe_wrusedw.d[] = wr_udwn[];
	dffpipe_ws_dgrp.clock = wrclk;
	dffpipe_ws_dgrp.clrn = tmp_aclr;
	dffpipe_ws_dgrp.d[] = tmp_data[];
	dffpipe_ws_nbrp.clock = wrclk;
	dffpipe_ws_nbrp.clrn = tmp_aclr;
	dffpipe_ws_nbrp.d[] = ws_nbrp[];
	lpm_add_sub_rd_udwn.dataa[] = rs_dbwp[];
	lpm_add_sub_rd_udwn.datab[] = rdptr_b.q[];
	lpm_add_sub_wr_udwn.dataa[] = wrptr_b.q[];
	lpm_add_sub_wr_udwn.datab[] = ws_dbrp[];
	rdptr_b.aclr = aclr;
	rdptr_b.clock = rdclk;
	rdptr_b.cnt_en = valid_rreq;
	wrptr_b.aclr = aclr;
	wrptr_b.clock = wrclk;
	wrptr_b.cnt_en = valid_wreq;
	q[] = fiforam.q[];
	rd_dbuw[] = dffpipe_rdbuw.q[];
	rd_udwn[] = lpm_add_sub_rd_udwn.result[];
	rdempty = read_state.empty;
	rdfull = read_state.full;
	rdusedw[] = dffpipe_rdusedw.q[];
	rs_dbwp[] = dffpipe_rs_dbwp.q[];
	rs_dgwp[] = dffpipe_rs_dgwp.q[];
	rs_nbwp[] = gray2bin_rs_nbwp.bin[];
	tmp_aclr = (! aclr);
	tmp_data[] = rdptrrg[].q;
	valid_rreq = rdreq;
	valid_wreq = wrreq;
	wr_dbuw[] = dffpipe_wr_dbuw.q[];
	wr_udwn[] = lpm_add_sub_wr_udwn.result[];
	wrempty = write_state.empty;
	wrfull = write_state.full;
	wrusedw[] = dffpipe_wrusedw.q[];
	ws_dbrp[] = dffpipe_ws_nbrp.q[];
	ws_dgrp[] = dffpipe_ws_dgrp.q[];
	ws_nbrp[] = gray2bin_ws_nbrp.bin[];
END;
--VALID FILE