scfifo_ek61.tdf

多功能卡的源代码

--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALMOST_FULL_VALUE=128 DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=8 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr almost_full clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 8.0 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_fifo_common 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_dpfifo_tj31 (aclr, clock, data[15..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[15..0], usedw[7..0]);

--synthesis_resources = lut 3 M4K 1 
SUBDESIGN scfifo_ek61
( 
	aclr	:	input;
	almost_full	:	output;
	clock	:	input;
	data[15..0]	:	input;
	empty	:	output;
	full	:	output;
	q[15..0]	:	output;
	rdreq	:	input;
	usedw[7..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_tj31;
	dffe_af : dffe;
	comparison_af0	: WIRE;
	comparison_af1	: WIRE;
	comparison_af2	: WIRE;
	comparison_af3	: WIRE;
	comparison_af4	: WIRE;
	comparison_af5	: WIRE;
	comparison_af6	: WIRE;
	comparison_af7	: WIRE;
	comparison_pre_af0	: WIRE;
	comparison_pre_af1	: WIRE;
	comparison_pre_af2	: WIRE;
	comparison_pre_af3	: WIRE;
	comparison_pre_af4	: WIRE;
	comparison_pre_af5	: WIRE;
	comparison_pre_af6	: WIRE;
	comparison_pre_af7	: WIRE;
	sclr	: NODE;
	wire_af[7..0]	: WIRE;
	wire_pre_af[7..0]	: WIRE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	dffe_af.clk = clock;
	dffe_af.clrn = (! aclr);
	dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af7 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af7) & wrreq) & (! rdreq))));
	almost_full = dffe_af.q;
	comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]);
	comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0);
	comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1);
	comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2);
	comparison_af4 = ((dpfifo.usedw[4..4] $ wire_af[4..4]) & comparison_af3);
	comparison_af5 = ((dpfifo.usedw[5..5] $ wire_af[5..5]) & comparison_af4);
	comparison_af6 = ((dpfifo.usedw[6..6] $ wire_af[6..6]) & comparison_af5);
	comparison_af7 = ((dpfifo.usedw[7..7] $ wire_af[7..7]) & comparison_af6);
	comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]);
	comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0);
	comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1);
	comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2);
	comparison_pre_af4 = ((dpfifo.usedw[4..4] $ wire_pre_af[4..4]) & comparison_pre_af3);
	comparison_pre_af5 = ((dpfifo.usedw[5..5] $ wire_pre_af[5..5]) & comparison_pre_af4);
	comparison_pre_af6 = ((dpfifo.usedw[6..6] $ wire_pre_af[6..6]) & comparison_pre_af5);
	comparison_pre_af7 = ((dpfifo.usedw[7..7] $ wire_pre_af[7..7]) & comparison_pre_af6);
	empty = dpfifo.empty;
	full = dpfifo.full;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
	wire_af[] = ( B"0", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
	wire_pre_af[] = ( B"1", B"0", B"0", B"0", B"0", B"0", B"0", B"0");
END;
--VALID FILE