ad_test.map.qmsg

多功能卡的源代码

{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(227) " "Warning (10273): Verilog HDL warning at dma_all.v(227): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 227 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(230) " "Warning (10273): Verilog HDL warning at dma_all.v(230): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 230 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(344) " "Warning (10273): Verilog HDL warning at dma_all.v(344): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 344 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(346) " "Warning (10273): Verilog HDL warning at dma_all.v(346): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 346 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(347) " "Warning (10273): Verilog HDL warning at dma_all.v(347): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 347 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dma_all.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dma_all.v" { { "Info" "ISGN_ENTITY_NAME" "1 dma_all " "Info: Found entity 1: dma_all" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_clk_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_clk_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 double_clk_fifo " "Info: Found entity 1: double_clk_fifo" {  } { { "double_clk_fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/double_clk_fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DS_ad_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DS_ad_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 DS_ad_ctrl " "Info: Found entity 1: DS_ad_ctrl" {  } { { "DS_ad_ctrl.v" "" { Text "C:/Users/liutong/Desktop/CPCI/DS_ad_ctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DS_ad_subctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DS_ad_subctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 DS_ad_subctrl " "Info: Found entity 1: DS_ad_subctrl" {  } { { "DS_ad_subctrl.v" "" { Text "C:/Users/liutong/Desktop/CPCI/DS_ad_subctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lt_uart_r5.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lt_uart_r5.v" { { "Info" "ISGN_ENTITY_NAME" "1 lt_uart_r5 " "Info: Found entity 1: lt_uart_r5" {  } { { "lt_uart_r5.v" "" { Text "C:/Users/liutong/Desktop/CPCI/lt_uart_r5.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.v" "" { Text "C:/Users/liutong/Desktop/CPCI/pll.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPCI_exp_bk.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CPCI_exp_bk.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPCI_exp_bk " "Info: Found entity 1: CPCI_exp_bk" {  } { { "CPCI_exp_bk.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp_bk.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_tran.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_tran.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_tran " "Info: Found entity 1: clk_tran" {  } { { "clk_tran.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_tran.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_fifo " "Info: Found entity 1: test_fifo" {  } { { "test_fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/test_fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NUM_TEST1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file NUM_TEST1.v" { { "Info" "ISGN_ENTITY_NAME" "1 NUM_TEST1 " "Info: Found entity 1: NUM_TEST1" {  } { { "NUM_TEST1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/NUM_TEST1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "14491.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 14491.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 14491 " "Info: Found entity 1: 14491" {  } { { "14491.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/14491.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CPCI_exp " "Info: Elaborating entity \"CPCI_exp\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "core1 core1:inst23 " "Info: Elaborating entity \"core1\" for hierarchy \"core1:inst23\"" {  } { { "CPCI_exp.bdf" "inst23" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { { 568 128 456 920 "inst23" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "core1.v(266) " "Info (10264): Verilog HDL Case Statement information at core1.v(266): all case item expressions in this case statement are onehot" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 266 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "RAM_BHE_ core1.v(174) " "Warning (10240): Verilog HDL Always Construct warning at core1.v(174): inferring latch(es) for variable \"RAM_BHE_\", which holds its previous value in one or more paths through the always construct" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 174 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "RAM_BLE_ core1.v(174) " "Warning (10240): Verilog HDL Always Construct warning at core1.v(174): inferring latch(es) for variable \"RAM_BLE_\", which holds its previous value in one or more paths through the always construct" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 174 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "RAM_CE1_ core1.v(174) " "Warning (10240): Verilog HDL Always Construct warning at core1.v(174): inferring latch(es) for variable \"RAM_CE1_\", which holds its previous value in one or more paths through the always construct" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 174 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "RAM_CE2 core1.v(174) " "Warning (10240): Verilog HDL Always Construct warning at core1.v(174): inferring latch(es) for variable \"RAM_CE2\", which holds its previous value in one or more paths through the always construct" {  } { { "core1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core1.v" 174 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}