a_dpfifo_6531.tdf

多功能卡的源代码

--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=9 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock data empty q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 8.0 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_fifo_common 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.


FUNCTION a_fefifo_s7f (aclr, clock, rreq, sclr, wreq)
RETURNS ( empty, full, usedw_out[8..0]);
FUNCTION dpram_cg01 (data[15..0], inclock, outclock, outclocken, rdaddress[8..0], wraddress[8..0], wren)
RETURNS ( q[15..0]);
FUNCTION cntr_0cb (aclr, clock, cnt_en, sclr)
RETURNS ( q[8..0]);

--synthesis_resources = lut 2 M4K 2 
SUBDESIGN a_dpfifo_6531
( 
	aclr	:	input;
	clock	:	input;
	data[15..0]	:	input;
	empty	:	output;
	q[15..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[8..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	fifo_state : a_fefifo_s7f;
	FIFOram : dpram_cg01;
	rd_ptr_count : cntr_0cb;
	wr_ptr : cntr_0cb;
	rd_ptr[8..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	fifo_state.aclr = aclr;
	fifo_state.clock = clock;
	fifo_state.rreq = rreq;
	fifo_state.sclr = sclr;
	fifo_state.wreq = wreq;
	FIFOram.data[] = data[];
	FIFOram.inclock = clock;
	FIFOram.outclock = clock;
	FIFOram.outclocken = (valid_rreq # sclr);
	FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]);
	FIFOram.wraddress[] = wr_ptr.q[];
	FIFOram.wren = valid_wreq;
	rd_ptr_count.aclr = aclr;
	rd_ptr_count.clock = clock;
	rd_ptr_count.cnt_en = valid_rreq;
	rd_ptr_count.sclr = sclr;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	empty = fifo_state.empty;
	q[] = FIFOram.q[];
	rd_ptr[] = rd_ptr_count.q[];
	usedw[] = fifo_state.usedw_out[];
	valid_rreq = (rreq & (! fifo_state.empty));
	valid_wreq = (wreq & (! fifo_state.full));
END;
--VALID FILE