prev_cmp_ad_test.map.qmsg

多功能卡的源代码

{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(346) " "Warning (10273): Verilog HDL warning at dma_all.v(346): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 346 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(347) " "Warning (10273): Verilog HDL warning at dma_all.v(347): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 347 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dma_all.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dma_all.v" { { "Info" "ISGN_ENTITY_NAME" "1 dma_all " "Info: Found entity 1: dma_all" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_clk_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_clk_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 double_clk_fifo " "Info: Found entity 1: double_clk_fifo" {  } { { "double_clk_fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/double_clk_fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DS_ad_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DS_ad_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 DS_ad_ctrl " "Info: Found entity 1: DS_ad_ctrl" {  } { { "DS_ad_ctrl.v" "" { Text "C:/Users/liutong/Desktop/CPCI/DS_ad_ctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DS_ad_subctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DS_ad_subctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 DS_ad_subctrl " "Info: Found entity 1: DS_ad_subctrl" {  } { { "DS_ad_subctrl.v" "" { Text "C:/Users/liutong/Desktop/CPCI/DS_ad_subctrl.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lt_uart_r5.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lt_uart_r5.v" { { "Info" "ISGN_ENTITY_NAME" "1 lt_uart_r5 " "Info: Found entity 1: lt_uart_r5" {  } { { "lt_uart_r5.v" "" { Text "C:/Users/liutong/Desktop/CPCI/lt_uart_r5.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.v" "" { Text "C:/Users/liutong/Desktop/CPCI/pll.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPCI_exp_bk.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CPCI_exp_bk.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPCI_exp_bk " "Info: Found entity 1: CPCI_exp_bk" {  } { { "CPCI_exp_bk.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp_bk.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_tran.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_tran.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_tran " "Info: Found entity 1: clk_tran" {  } { { "clk_tran.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_tran.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_fifo " "Info: Found entity 1: test_fifo" {  } { { "test_fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/test_fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NUM_TEST1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file NUM_TEST1.v" { { "Info" "ISGN_ENTITY_NAME" "1 NUM_TEST1 " "Info: Found entity 1: NUM_TEST1" {  } { { "NUM_TEST1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/NUM_TEST1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "14491.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 14491.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 14491 " "Info: Found entity 1: 14491" {  } { { "14491.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/14491.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "_422_receiver_2 " "Info: Elaborating entity \"_422_receiver_2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "_422_receiver_2.v(76) " "Info (10264): Verilog HDL Case Statement information at _422_receiver_2.v(76): all case item expressions in this case statement are onehot" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 76 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|_422_receiver_2\|state 3 " "Info: State machine \"\|_422_receiver_2\|state\" contains 3 states" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|_422_receiver_2\|state " "Info: Selected Auto state machine encoding method for state machine \"\|_422_receiver_2\|state\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|_422_receiver_2\|state " "Info: Encoding result for state machine \"\|_422_receiver_2\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.01 " "Info: Encoded state bit \"state.01\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.11 " "Info: Encoded state bit \"state.11\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.00 " "Info: Encoded state bit \"state.00\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|_422_receiver_2\|state.00 000 " "Info: State \"\|_422_receiver_2\|state.00\" uses code string \"000\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|_422_receiver_2\|state.01 101 " "Info: State \"\|_422_receiver_2\|state.01\" uses code string \"101\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|_422_receiver_2\|state.11 011 " "Info: State \"\|_422_receiver_2\|state.11\" uses code string \"011\"" {  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0}  } { { "_422_receiver_2.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_receiver_2.v" 19 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state.01 " "Info: Register \"state.01\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "state.11 " "Info: Register \"state.11\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/liutong/Desktop/CPCI/ad_test.map.smsg " "Info: Generated suppressed messages file C:/Users/liutong/Desktop/CPCI/ad_test.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "43 " "Info: Implemented 43 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "29 " "Info: Implemented 29 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "184 " "Info: Peak virtual memory: 184 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 23 21:33:19 2009 " "Info: Processing ended: Mon Mar 23 21:33:19 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}