prev_cmp_ad_test.map.qmsg

多功能卡的源代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_422_to_fifo4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file _422_to_fifo4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 _422_to_fifo4 " "Info: Found entity 1: _422_to_fifo4" {  } { { "_422_to_fifo4.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/_422_to_fifo4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "_422_txd.v(14) " "Warning (10268): Verilog HDL information at _422_txd.v(14): always construct contains both blocking and non-blocking assignments" {  } { { "_422_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_txd.v" 14 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_422_txd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _422_txd.v" { { "Info" "ISGN_ENTITY_NAME" "1 _422_txd " "Info: Found entity 1: _422_txd" {  } { { "_422_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_txd.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "_422_txd1.v(22) " "Warning (10268): Verilog HDL information at _422_txd1.v(22): always construct contains both blocking and non-blocking assignments" {  } { { "_422_txd1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_txd1.v" 22 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_422_txd1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _422_txd1.v" { { "Info" "ISGN_ENTITY_NAME" "1 _422_txd1 " "Info: Found entity 1: _422_txd1" {  } { { "_422_txd1.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_txd1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_422_txd_power.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _422_txd_power.v" { { "Info" "ISGN_ENTITY_NAME" "1 _422_txd_power " "Info: Found entity 1: _422_txd_power" {  } { { "_422_txd_power.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_422_txd_power.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_7301fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _7301fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 _7301fifo " "Info: Found entity 1: _7301fifo" {  } { { "_7301fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_7301fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_7864fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _7864fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 _7864fifo " "Info: Found entity 1: _7864fifo" {  } { { "_7864fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_7864fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "_back_fifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file _back_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 _back_fifo " "Info: Found entity 1: _back_fifo" {  } { { "_back_fifo.v" "" { Text "C:/Users/liutong/Desktop/CPCI/_back_fifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad7864_fifo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad7864_fifo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ad7864_fifo " "Info: Found entity 1: ad7864_fifo" {  } { { "ad7864_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/ad7864_fifo.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad_test_new.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad_test_new.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ad_test_new " "Info: Found entity 1: ad_test_new" {  } { { "ad_test_new.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/ad_test_new.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adt7301_fifo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adt7301_fifo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adt7301_fifo " "Info: Found entity 1: adt7301_fifo" {  } { { "adt7301_fifo.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/adt7301_fifo.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altpll0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file altpll0.v" { { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.v" "" { Text "C:/Users/liutong/Desktop/CPCI/altpll0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_txd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_txd.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_txd " "Info: Found entity 1: clk_txd" {  } { { "clk_txd.v" "" { Text "C:/Users/liutong/Desktop/CPCI/clk_txd.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "core.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file core.v" { { "Info" "ISGN_ENTITY_NAME" "1 core " "Info: Found entity 1: core" {  } { { "core.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "core_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file core_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 core_controller " "Info: Found entity 1: core_controller" {  } { { "core_controller.v" "" { Text "C:/Users/liutong/Desktop/CPCI/core_controller.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPCI_exp.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CPCI_exp.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPCI_exp " "Info: Found entity 1: CPCI_exp" {  } { { "CPCI_exp.bdf" "" { Schematic "C:/Users/liutong/Desktop/CPCI/CPCI_exp.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma.v(232) " "Warning (10273): Verilog HDL warning at dma.v(232): extended using \"x\" or \"z\"" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 232 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma.v(233) " "Warning (10273): Verilog HDL warning at dma.v(233): extended using \"x\" or \"z\"" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 233 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma.v(234) " "Warning (10273): Verilog HDL warning at dma.v(234): extended using \"x\" or \"z\"" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 234 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dma.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dma.v" { { "Info" "ISGN_ENTITY_NAME" "1 dma " "Info: Found entity 1: dma" {  } { { "dma.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(227) " "Warning (10273): Verilog HDL warning at dma_all.v(227): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 227 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(230) " "Warning (10273): Verilog HDL warning at dma_all.v(230): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 230 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "dma_all.v(344) " "Warning (10273): Verilog HDL warning at dma_all.v(344): extended using \"x\" or \"z\"" {  } { { "dma_all.v" "" { Text "C:/Users/liutong/Desktop/CPCI/dma_all.v" 344 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}