📄 altpll0_waveforms.html
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<title>Sample Waveforms for altpll0.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file altpll0.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.v. The design altpll0.v has Cyclone AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 30303 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
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