core_controller.v

多功能卡的源代码

/*===============================================================================================*/
/*416陈利彬编制                                                                                  */
/*修改于11月21日13：29                                                                           */
/*需要修改读空信号，原来读空信号是低有效，现在是高表示读空                                       */
/*===============================================================================================*/
module core_controller(RHF_ONE_,   //422 channel one half full
		RFE_ONE_,                  //422第一路fifo读空
		RD_FIFO_ONE,               //读422第一路fifo控制信号
		RHF_TWO_,                  //422第一路fifo半满
		RFE_TWO_,                  //422第二路fifo读空
		RD_FIFO_TWO,               //读422第二路fifo控制信号
		RHF_THREE_,                //422第二路fifo半满
		RFE_THREE_,
		RD_FIFO_THREE,
		RHF_FORE_,
		RFE_FORE_,
		RD_FIFO_FORE,
		RHF_232_,
		RFE_232_,
		RD_FIFO_232,
		/////////////////////////////////////////////
		CLK,
		reset_,
		busy_flag,
		////////////////////////////////////////////
		//ad7864_HF_,
		//ad7864_EM_,
		//ds_7864fifo_rd,
		//ad7301_HF_,			   
        //ad7301_EM_,
        //ds_7301fifo_rd,
        //ds_12io_rd,
        ////////////////////////////////////////////
        //pci_read_ad7864,//pci总线读AD7864的FIFO标志位，如果此位为1，则触发普通方式读FIFO
        //pci_read_ad7301,//pci总线读AD7301的FIFO标志位，如果此位为1，则触发普通方式读FIFO
        //pci_read_12io,//pci总线读12路IO的标志位，如果此位为1，则触发普通方式读12路IO的寄存器
        pci_read_flag,//pci总线读ram标志位，如果此位为1，则触发DMA方式读ram
        ///////////////////////////////////////////
        operate_state,
        D422_c1_fe,
        dma_finish_flag,//DMA结束标志，LA写入该标志，表示此次DMA结束，清零地址寄存器
        current_state,
        RAM_ADDR_COUNTER1,//输出给PCI总线的地址计数器的数值
        data_to_ram_en,//如果各路fifo输出给ram的信号有效，则此位=1；否则此位==0
        data_to_ld_en,//ram输出给LD的数值有效位，为了匹配DMA的时序，数据有效时，该位==1；否则==0
        //RAM  的控制信号
        RAM_ADDR,
        RAM_CE1_,
        RAM_CE2,
        RAM_BHE_,
        RAM_BLE_,
        RAM_WE_,
		fifo_sel
);
input CLK;
input reset_;
input dma_finish_flag;
//422 and 232 FIFO控制和状态信号
input RHF_ONE_;                    //422第一路fifo半满
input RFE_ONE_;                    //422第一路fifo读空
output RD_FIFO_ONE;                //读422第一路fifo控制信号
reg RD_FIFO_ONE;
input RHF_TWO_;
input RFE_TWO_;
output RD_FIFO_TWO;
reg RD_FIFO_TWO;
input RHF_THREE_;
input RFE_THREE_;
output RD_FIFO_THREE;
reg RD_FIFO_THREE;
input RHF_FORE_;
input RFE_FORE_;
output RD_FIFO_FORE;
reg RD_FIFO_FORE;
input RHF_232_;
input RFE_232_;
output RD_FIFO_232;
reg RD_FIFO_232;
//RAM的控制信号
output RAM_CE1_;
output RAM_CE2;
output RAM_BHE_;
output RAM_BLE_;
output RAM_WE_;
output [19:0] RAM_ADDR;              //20bit width
reg RAM_CE1_;
reg RAM_CE2;
reg RAM_BHE_;
reg RAM_BLE_;
reg RAM_WE_;
reg [19:0] RAM_ADDR;              //20bit width
//AD的FIFO状态和控制信号  and 12路IO的
//input ad7864_HF_;
//input ad7864_EM_;
//input ad7301_HF_;
//input ad7301_EM_;
/*output ds_7864fifo_rd;
output ds_7301fifo_rd;
output ds_12io_rd;
reg ds_7864fifo_rd;
reg ds_7301fifo_rd;
reg ds_12io_rd;*/
//输出数据有效的标志
output data_to_ram_en;
reg data_to_ram_en;
output data_to_ld_en;
reg data_to_ld_en;
///////////////////////////////////////////////
                    
reg [6:0] state;//bit 7 width
parameter  p422_channel_oneram_firstaddr =   20'b0000_0000_0000_0000_0001;//10_0000_0000_0000_0000
//繁忙标志信号，表示总线正在被占用
reg busy_flag;
output busy_flag;
/////////////////////////////////////

//地址计数器,用于地址对LD输出
reg [19:0] RAM_ADDR_COUNTER1;
output [19:0] RAM_ADDR_COUNTER1;
//读地址计数器，用于标志LD的DMA方式读到RAM的哪一个地址
reg [19:0] RAM_ADDR_COUNTER11;
//================================================================================================//
reg [1:0] current_state;
output [1:0] current_state;
reg [1:0] next_state;
wire half_full_state;
assign half_full_state = RHF_ONE_ && RHF_TWO_ && RHF_THREE_ && RHF_FORE_ && RHF_232_;
reg [4:0] operate_state;
output [4:0] operate_state;
//reg [1:0] operate_state_read;
/*
reg operate_state_readad1;
reg operate_state_readad2;
reg operate_state_read12io;
*/
//如果任意一路fifo半满，则half_full_state状态为0，表示半满，准备开始工作
reg D422_c1_fe;
output D422_c1_fe;
reg D422_c2_fe;
reg D422_c3_fe;
reg D422_c4_fe;
reg D232_fe;

/////////////////////////////////////
output [4:0]fifo_sel;
reg [4:0]fifo_sel;
/////////////////////////////////////
always @(negedge CLK or negedge reset_)
begin//1
	if(!reset_)begin
		RAM_BHE_ <= 1'b0;        //RAM_BHE_ is enable always
		RAM_BLE_ <= 1'b0;        //RAM_BLE_ is enable always
		RAM_WE_ <= 1'b1;
		RAM_CE1_ <= 1'b1;                     
		RAM_CE2 <= 1'b0;
		operate_state <= 5'h0;
		RAM_ADDR <= 20'h0;
		busy_flag <= 1'b0;

		RAM_ADDR_COUNTER1 <= 20'h0;//5地址计数器初始化

		RAM_ADDR_COUNTER11 <= 20'h0;//5地址计数器初始化

		//ds_7864fifo_rd <= 1'b1;
		//ds_7301fifo_rd <= 1'b1;
		RD_FIFO_ONE <= 1'b0;
		RD_FIFO_TWO <= 1'b0;
		RD_FIFO_THREE <= 1'b0;
		RD_FIFO_FORE <= 1'b0;
		RD_FIFO_232 <= 1'b0;

		//operate_state_readad1 <= 1'b0;
		//operate_state_readad2 <= 1'b0;
		//operate_state_read12io <= 1'b0;
		D422_c1_fe <= 1'b1;
		D422_c2_fe <= 1'b1;
		D422_c3_fe <= 1'b1;
		D422_c4_fe <= 1'b1;
		D232_fe <= 1'b1;
		data_to_ram_en <= 1'b0; 
		data_to_ld_en <= 1'b0;
		
		fifo_sel<=5'b11111;
	end
	else begin//2
		casex(current_state)
		3'd0:begin
			busy_flag <= 1'b0;//没有任何处理 busy == 0
			operate_state <= 5'd0;//
		end
		3'd1:begin//fifo半满了，从第一路到第四路，开始一次向ram里面写数据，然后地址自加一
			case(operate_state)
			5'd0:begin//这里应该首先加入判断，防止只有一路422工作的bug
					busy_flag <= 1'b1;//busy == 1
					data_to_ld_en <= 1'b0;
					data_to_ram_en <= 1'b1;//表示模块正在向RAM写数据
				if(RFE_ONE_ == 1)begin//表示fifo没有被读空
					operate_state <= 5'd1;//进入状态1
					RD_FIFO_ONE <= 1'b0;//收回读fifo信号
				end
				else begin//如果fifo被读空了
					RD_FIFO_ONE <= 1'b0;
					fifo_sel[1]<=1'b1;
					operate_state <= 5'd4;//进入状态4
				end
			end
			5'd1:begin
				if(RFE_ONE_ == 1)begin
					RAM_ADDR <= p422_channel_oneram_firstaddr + RAM_ADDR_COUNTER1;//放入地址=首地址+计数器
					RAM_ADDR_COUNTER1 <= RAM_ADDR_COUNTER1 + 20'b01;//计数器+1//eulerhit
					RAM_CE1_ <= 1'b0;//加入写ram控制信号3个
					RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd2;
					//*****************************
					fifo_sel[1]<=1'b0;
				end
				else begin
					RD_FIFO_ONE <= 1'b0;
					fifo_sel[1]<=1'b1;
					operate_state <= 5'd4;//进入状态4
				end
			end
			5'd2:begin
				D422_c1_fe <= RFE_ONE_;//不过这里没有使用到这一位标志
				operate_state <= 5'd3;//进入状态3
			end
			5'd3:begin
				RAM_CE1_ <= 1'b1;//拉高ram控制信号
				RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd0;//进入状态0
				RD_FIFO_ONE <= 1'b1;//给出读fifo信号，该信号高有效
			end
			//==================================================================================//
			5'd4:begin//这里应该首先加入判断，防止只有一路422工作的bug
				if(RFE_TWO_ == 1)begin                    //如果fifo没有被读空
					operate_state <= 5'd5;//进入状态5
					RD_FIFO_TWO <= 1'b0;  
				end
				else begin//如果fifo被读空了
					RD_FIFO_TWO <= 1'b0;
					fifo_sel[2]<=1'b1;
					operate_state <= 5'd8;//进入状态8
				end
			end
			5'd5:begin
			if(RFE_TWO_ == 1)begin                    //如果fifo没有被读空
					RAM_ADDR <= p422_channel_oneram_firstaddr + RAM_ADDR_COUNTER1;//放入地址=首地址+计数器
					RAM_ADDR_COUNTER1 <= RAM_ADDR_COUNTER1 + 20'b01;//计数器+1//eulerhit
					RAM_CE1_ <= 1'b0;                     //加入写ram控制信号3个
					RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd6;  
					//*****************************
					fifo_sel[2]<=1'b0;
				end
			else begin//如果fifo被读空了
					RD_FIFO_TWO <= 1'b0;
					fifo_sel[2]<=1'b1;
					operate_state <= 5'd8;//进入状态8
				end
				
			end