📄 _422_txd4.v.bak
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module _422_txd4(sclk_2x,
reset,
sdout,
sclk_out
);
input sclk_2x,reset;
output sclk_out,sdout;
reg sdout;
reg [7:0]data_txd;
reg [3:0]counter;
reg sclk_out;
always @(posedge sclk_2x or negedge reset)
begin
if(!reset)
begin
data_txd=8'b1001_0011;
counter<=4'b0;
sdout<=data_txd[0];
sclk_out<=1'b0;
end
else
begin
case (counter)
4'b0000:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b0001://1th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[1];
counter[1]<=~counter[1];
end
4'b0011:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b0010://2th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[2];
counter[2]<=~counter[2];
end
4'b0110:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b0111://3th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[3];
counter[1]<=~counter[1];
end
4'b0101:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b0100://4th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[4];
counter[3]<=~counter[3];
end
4'b1100:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b1101://5th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[5];
counter[1]<=~counter[1];
end
4'b1111:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b1110://6th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[6];
counter[2]<=~counter[2];
end
4'b1010:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b1011://7th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[7];
counter[1]<=~counter[1];
end
4'b1001:
begin
sclk_out<=1'b1;
counter[0]<=~counter[0];
end
4'b1000://0th bit
begin
sclk_out<=1'b0;
sdout<=data_txd[0];
counter[3]<=~counter[3];
end
endcase
end
end
endmodule
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