📄 core1.bsf
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "core1" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 336 25 348)(font "Arial" ))
(port
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)
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(text "RFE_ONE_" (rect 0 0 57 12)(font "Arial" ))
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(port
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(input)
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(text "RHF_THREE_" (rect 21 91 92 103)(font "Arial" ))
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(port
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(port
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(text "CLK" (rect 21 187 42 199)(font "Arial" ))
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(text "write_allow" (rect 21 235 72 247)(font "Arial" ))
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)
(port
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(input)
(text "dma_finish_flag" (rect 0 0 79 12)(font "Arial" ))
(text "dma_finish_flag" (rect 21 251 100 263)(font "Arial" ))
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)
(port
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(text "RD_FIFO_ONE" (rect 230 27 307 39)(font "Arial" ))
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(port
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(text "RD_FIFO_THREE" (rect 217 59 307 71)(font "Arial" ))
(line (pt 328 64)(pt 312 64)(line_width 1))
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(port
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(text "RD_FIFO_FORE" (rect 223 75 307 87)(font "Arial" ))
(line (pt 328 80)(pt 312 80)(line_width 1))
)
(port
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)
(port
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(output)
(text "RAM_ADDR[19..0]" (rect 0 0 93 12)(font "Arial" ))
(text "RAM_ADDR[19..0]" (rect 214 155 307 167)(font "Arial" ))
(line (pt 328 160)(pt 312 160)(line_width 3))
)
(port
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(output)
(text "RAM_OE_" (rect 0 0 50 12)(font "Arial" ))
(text "RAM_OE_" (rect 257 171 307 183)(font "Arial" ))
(line (pt 328 176)(pt 312 176)(line_width 1))
)
(port
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(output)
(text "RAM_CE1_" (rect 0 0 56 12)(font "Arial" ))
(text "RAM_CE1_" (rect 251 187 307 199)(font "Arial" ))
(line (pt 328 192)(pt 312 192)(line_width 1))
)
(port
(pt 328 208)
(output)
(text "RAM_CE2" (rect 0 0 50 12)(font "Arial" ))
(text "RAM_CE2" (rect 257 203 307 215)(font "Arial" ))
(line (pt 328 208)(pt 312 208)(line_width 1))
)
(port
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(output)
(text "RAM_BHE_" (rect 0 0 57 12)(font "Arial" ))
(text "RAM_BHE_" (rect 250 219 307 231)(font "Arial" ))
(line (pt 328 224)(pt 312 224)(line_width 1))
)
(port
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(output)
(text "RAM_BLE_" (rect 0 0 55 12)(font "Arial" ))
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(text "RAM_WE_" (rect 0 0 53 12)(font "Arial" ))
(text "RAM_WE_" (rect 254 251 307 263)(font "Arial" ))
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(output)
(text "fifo_sel[4..0]" (rect 0 0 63 12)(font "Arial" ))
(text "fifo_sel[4..0]" (rect 244 267 307 279)(font "Arial" ))
(line (pt 328 272)(pt 312 272)(line_width 3))
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(port
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(output)
(text "read_bkfifo_request" (rect 0 0 99 12)(font "Arial" ))
(text "read_bkfifo_request" (rect 208 283 307 295)(font "Arial" ))
(line (pt 328 288)(pt 312 288)(line_width 1))
)
(port
(pt 328 304)
(output)
(text "RAM_READ_ADDR_POINTER[31..0]" (rect 0 0 184 12)(font "Arial" ))
(text "RAM_READ_ADDR_POINTER[31..0]" (rect 123 299 307 311)(font "Arial" ))
(line (pt 328 304)(pt 312 304)(line_width 3))
)
(port
(pt 328 320)
(output)
(text "RAM_WRITE_ADDR_POINTER[31..0]" (rect 0 0 188 12)(font "Arial" ))
(text "RAM_WRITE_ADDR_POINTER[31..0]" (rect 119 315 307 327)(font "Arial" ))
(line (pt 328 320)(pt 312 320)(line_width 3))
)
(parameter
"time_delay"
"B\"00100100111111011011\""
""
)
(drawing
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)
(annotation_block (parameter)(rect 344 -64 444 16))
)
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