_422_receiver_2.v

多功能卡的源代码

//同步串口接收模块
//原作者：刘通
//
//
//		
module _422_receiver_2(reset,sdin,sys_clock,sclk,r_enable
						,dout,wrn
					);

input reset,sdin,sys_clock,sclk,r_enable;
output wrn;
output [7:0]dout;
//-------------------------------------
reg wrn;
reg [7:0]dout;
reg [7:0]data;
reg [2:0]bit_counter;
reg data_receive_begin;
reg [1:0]state;
/*
///////////////////////////////////////////////////////////
wire bit_counter_or;
reg bit_counter_or_reg;
reg data_receive_begin_reg;
assign bit_counter_or=|bit_counter;
*/
///////////////////////////////////////////////////////////
reg sclk_reg1;
reg sclk_reg2;
reg sdin_reg1;
always @(posedge sys_clock)
begin
	sclk_reg1 <= sclk;
	sclk_reg2 <= sclk_reg1;
	sdin_reg1 <= sdin;
end
always @(posedge sys_clock or negedge reset)
begin
	if(!reset)
	begin
		data <= 8'd0;
		bit_counter<=3'd0;
		data_receive_begin<=1'b0;
	end
	else if(r_enable)
	begin
		if( (sclk_reg1==0) && (sclk_reg2==1) )
		begin
			data[7:0]<={data[6:0],sdin_reg1};
			bit_counter<=bit_counter+3'd1;
			data_receive_begin<=1'b1;
		end
		else 
		begin
			data <= data;
			bit_counter<=bit_counter;
			data_receive_begin<=data_receive_begin;
		end
	end
	else 
	begin
		data <= 8'd0;
		bit_counter<=3'd0;
		data_receive_begin<=1'b0;
	end
end
always @(posedge sys_clock or negedge reset)
begin
	if(!reset)	
	begin
		dout<=8'd0;
		wrn<=1'b0;
		state<=2'b00;
	end
	else if((bit_counter==3'd0)&&(data_receive_begin==1'b1))
		case(state)
			2'b00:	
			begin	
				dout<=data;
				wrn<=1'b1;
				state<=2'b01;
			end
			2'b01: 	
			begin	
				wrn<=1'b0;
				state<=2'b11;	
			end
			default:	
			begin	
				state<=state;
				wrn<=1'b0;
			end
		endcase
	else	
	begin
		dout<=dout;
		wrn<=1'b0;
		state<=2'b00;
	end
end
/*
///////////////////////////////////////////////////////////
always @(negedge sclk or negedge reset)
begin
	if (!reset)	
		data<=8'b0;	
	else if(r_enable)
		data[7:0]<={sdin,data[7:1]};
	else 
		data<=8'b0;	
end
/////////////////////////////////////////////////////////
always @(negedge sclk or negedge reset)
begin
	if (!reset)	
		bit_counter<=3'd0;	
	else if(r_enable)
		bit_counter<=bit_counter+3'd1;
	else 
		bit_counter<=3'd0;
end
/////////////////////////////////////////////////////////
always @(negedge sclk or negedge reset)
begin
	if (!reset)	
		data_receive_begin<=1'b0;	
	else if(r_enable)
		data_receive_begin<=1'b1;
	else 
		data_receive_begin<=1'b0;
end
/////////////////////////////////////////////////////////
always @(posedge sys_clock)
begin
	bit_counter_or_reg<=bit_counter_or;
	data_receive_begin_reg<=data_receive_begin;
end
always @(posedge sys_clock or negedge reset)
begin
	if(!reset)	
	begin
		dout<=8'd0;
		wrn<=1'b0;
		state<=2'b00;
	end
	else if((bit_counter_or_reg==1'b0)&&(data_receive_begin_reg==1'b1))
		case(state)
			2'b00:	
			begin	
				dout<=data;
				wrn<=1'b1;
				state<=2'b01;
			end
			2'b01: 	
			begin	
				wrn<=1'b0;
				state<=2'b11;	
			end
			default:	
			begin	
				state<=state;
				wrn<=1'b0;
			end
		endcase
	else	
	begin
		dout<=8'd0;
		wrn<=1'b0;
		state<=2'b00;
	end
end
*/
//-------------------------------------------------------
////////////////////////////////////////////////////////
endmodule