dma.v

多功能卡的源代码

module dma(
               CLK,
               LA,
               LD,
               LHOLD,
               LHOLDA,
               LWR,
               READY_,
               ADS_,
               BLAST_,
				
               LRESET_,
               read_bkfifo_start,
			   //read_ram_start,
			   //write_ram_start,
               rd_7864_fifo,
               rd_7301_fifo,
               rd_12channel_io,
               reset_by_hand_,
               TOTAL_NUM_RECEIVED,
			   TOTAL_NUM_BE_READED,
			   _232_fifo_num,
				_9600_sel,
				_19200_sel,
				rd_232_direct,
				read_bkfifo_request
				//test_module
               );
//测试模块，LA==13，触发写RAM模块开始工作，再次触发LA==13，写RAM结束
//LA==14，读RAM开始，触发DMA
//LA==0，复位控制模块
// PCI LOCAL PINS block ==============================
input [8:0]_232_fifo_num;
input [31:0] TOTAL_NUM_RECEIVED;
input [31:0] TOTAL_NUM_BE_READED;
input CLK;
input [9:2] LA;
input LHOLD;
input LWR;
input ADS_;
input BLAST_;
input LRESET_;
//_7864&_7301 input pins

//communication(422&232) input pins

//inout pins
inout [31:0] LD;
output read_bkfifo_start;
output read_bkfifo_request;
//communication(422&232) output pins
output _9600_sel,_19200_sel;
//DMA pins
output LHOLDA;
output READY_;
output reset_by_hand_;
//output test_module;
//output [15:0] state;
/*
//core_controller pins
output RAM_CE1_VALID_;
output RAM_CE2_VALID;
output RAM_WE_VALID_;
output [19:0] RAM_ADDR_VALID;*/

//output sdramFifoWriteLock;
//_7864&_7301&_12io control pins
output rd_7864_fifo;
output rd_7301_fifo;
output rd_12channel_io;
output rd_232_direct;
//---------------------
//output read_ram_start;
//output write_ram_start;
//output data_en;
//output data_input;
//output [15:0] o_ram_data;
//output [15:0] ram_data_buf;
//output [4:0] operate_state;
///write_ram pins
///////////////////////////////////////////////////////
wire read_bkfifo_start;
wire read_bkfifo_request;
//wire write_ram_start;
//wire read_ram_start;
//wire[19:0] LD;

reg LHOLDA;
reg READY_;


wire rd_7864_fifo;
wire rd_7301_fifo;
wire rd_12channel_io;
wire pci_read_ram;
///////////////////////////////
//////////////////////////////
//wire data_en;
//wire data_input;
//wire [15:0] o_ram_data;
//wire [15:0] ram_data_buf;
//wire RAM_OE_;
//wire [19:0] counter_output;
//wire read_counter_ena;
// Other internal variable ===
wire reset_by_hand_;
//wire reset_fifo;
// write_ram input&output =====
// pci interface block ==============================

always @(posedge CLK)
if (LHOLD)
    LHOLDA =1'b1;
else
	LHOLDA =1'b0;

reg [3:0] currentstate;
reg [3:0] nextstate;

parameter s0 = 4'd0, // idle 
          s1 = 4'd1, // cycle start
          s2 = 4'd2, // single cycle wait state
          s3 = 4'd3, // single cycle last state
          s4 = 4'd4, // burst cycle wait state 
          s5 = 4'd5, // burst cycle repeat state 
          s6 = 4'd6; // burst cycle last state

reg DATA_CTL_;

always @ (*)
casex (currentstate)
s0: if (!ADS_  ) 
    nextstate = s1;
    else
	nextstate = s0;

s1: if (!BLAST_)
    nextstate = s2;
	else if (BLAST_)
	nextstate = s4;
	else 
	nextstate = s1;

s2: nextstate = s3;

s3: if (!ADS_)
	nextstate = s1;
	else
	nextstate = s0;
						
s4:	nextstate = s5;
		
s5:	if (BLAST_)
	nextstate = s5;
	else
	nextstate = s6;

s6:	if (!ADS_)
    nextstate = s1;
	else
	nextstate = s0;
endcase

always @ (currentstate)
		
casex(currentstate)
s0: begin
	READY_ =1'b1;
	DATA_CTL_=1'b1;
    end

s1: begin
	READY_ =1'b1;
	DATA_CTL_=1'b1;
	end
	
s2:	begin
	READY_=1'b0;
	DATA_CTL_=1'b0;
	end
	
s3:	begin
	READY_=1'b1;
	DATA_CTL_=1'b1;
	end
	
s4:	begin
	READY_=1'b0;
	DATA_CTL_=1'b0;
	end
	
s5:	begin
	READY_=1'b0;
	DATA_CTL_=1'b0;
	end
	
s6:	begin
	READY_=1'b1;
	DATA_CTL_=1'b1;
	end
	endcase
	
always @(posedge CLK)
    currentstate <= nextstate;
//reg [7:2] LA_BUF;
/*always @ (posedge CLK)
    LA_BUF <= LA;	*/	
//assign LD = (data_input | read_ram_start)?(RAM_D):20'hz;
//assign LD = ( read_counter_ena )?/*counter_output*/(RAM_ADDR_COUNTER_VALID):16'hz;
//assign LD = ( read_counter_ena )?/*counter_output*/{busy_flag,RAM_ADDR_COUNTER_VALID[18:0]}:20'hz;
//assign LD = ( read_state_ena )?(state):20'hz;

assign reset_by_hand_=((LA[7:2]==6'b011111/*011_111 = 3_7*/)&&(READY_==1'b0))?1'b0:1'b1;//7c
//assign pci_read_ram= ((LA[7:2]==6'b100001/*100_001 = 4_1*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//84
assign rd_7864_fifo= ((LA[7:2]==6'b110100/*110_100 = 6_4*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//D0 
assign rd_7301_fifo= ((LA[7:2]==6'b111011/*111_011 = 7_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//Ec 
assign rd_12channel_io= ((LA[7:2]==6'b001010/*001_010 = 1_2*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//28 
//assign write_ram_start = ((LA[7:2]==6'b111000/*111_000 = 7_0*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//E0 
//assign read_ram_start = ((LA[7:2]==6'b000111/*000_111 = 0_7*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//1F 

//assign read_counter_ena = ((LA[7:2]==6'b101101/*101_101 = 5_5*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//B7 
//assign read_state_ena = ((LA[7:2]==6'b110110/*110_110 = 6_6*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//DB 
//assign dma_finish_flag = ((LA[7:2]==6'b101001/*100_001 = 4_1*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//a4
//assign rd_422_ram_two= ((LA[7:2]==6'b100010/*100_010 = 4_2*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//88 
//assign rd_422_ram_three= ((LA[7:2]==6'b100011/*100_011 = 4_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//8c 
//assign rd_422_ram_fore= ((LA[7:2]==6'b100100/*100_100 = 4_4*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//90 
assign rd_232_direct= ((LA[7:2]==6'b010011/*010_011 = 2_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//4c 
//assign RESET_ = ((LA[5:2]==4'd15)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1; 
assign _9600_sel=((LA[7:2]==6'b010001)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1;//44
assign _19200_sel=((LA[7:2]==6'b010010)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b0 : 1'b1;//48
assign read_bkfifo_request=((LA[7:2]==6'b100011)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//8C
assign LD=((LA[7:2]==6'b100000)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?(TOTAL_NUM_RECEIVED) : 32'hz;//80
assign LD=((LA[7:2]==6'b100010)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?(TOTAL_NUM_BE_READED) : 32'hz;//88
assign LD=((LA[7:2]==6'b000110)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?(_232_fifo_num) : 32'hz;//18
//assign read_bkfifo_start=((LA[7:2]==6'b000001)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1:1'b0;//04
assign read_bkfifo_start=((LA[7:2]==6'b000111)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1:1'b0;//1f
////////////////////////////////////////////////////////
//assign test_module= ((LA[7:2]==6'b110011/*010_011 = 2_3*/)&&(DATA_CTL_==1'b0)&&(LWR==1'b0))?1'b1 : 1'b0;//cc
///////////////load core_controller/////////////////////
/*
core_controller core_controller(
        .RHF_ONE_(RHF_ONE_),//422_1
        .RFE_ONE_(RFE_ONE_),
        .RD_FIFO_ONE(RD_FIFO_ONE),
        .RHF_TWO_(RHF_TWO_),//422_2
        .RFE_TWO_(RFE_TWO_),
        .RD_FIFO_TWO(RD_FIFO_TWO),
        .RHF_THREE_(RHF_THREE_),//422_3
        .RFE_THREE_(RFE_THREE_),
        .RD_FIFO_THREE(RD_FIFO_THREE),
        .RHF_FORE_(RHF_FORE_),//422_4
		.RFE_FORE_(RFE_FORE_),
		.RD_FIFO_FORE(RD_FIFO_FORE),
		.RHF_232_(RHF_232_),//232
		.RFE_232_(RFE_232_),
		.RD_FIFO_232(RD_FIFO_232),
		.CLK(CLK),
		.reset_(reset_by_hand_),//input
		.busy_flag(busy_flag),
		.pci_read_flag(pci_read_ram),
		.operate_state(operate_state),
		.D422_c1_fe(D422_c1_fe),
		.dma_finish_flag(dma_finish_flag),//用来清零地址计数器//DMA结束标志，LA写入该标志，表示此次DMA结束，清零地址寄存器
		.current_state(current_state_1),//此路为422读写ram模块的当前状态，不同于pci状态控制的当前状态
		.RAM_ADDR_COUNTER1(RAM_ADDR_COUNTER_VALID),
		.data_to_ram_en(data_to_ram_en),
		.data_to_ld_en(data_to_ld_en),
		.RAM_ADDR(RAM_ADDR_VALID),
		.RAM_CE1_(RAM_CE1_VALID_),
		.RAM_CE2(RAM_CE2_VALID),
		.RAM_BHE_(RAM_BHE_),
		.RAM_BLE_(RAM_BLE_),
		.RAM_WE_(RAM_WE_VALID_),
		.fifo_sel(fifo_sel)
);*/
////////////////////////////////////////////////////////
/*
问题所在是RAM_ADDR,RAM_CE1_,RAM_CE2,RAM_BHE_,RAM_BLE_,RAM_WE_,RAM_OE_这几个信号的连接分配问题

*/
////////////////////////////////////////////////////////
endmodule