core.v

多功能卡的源代码

					//*****************************
					fifo_sel[1]<=1'b0;
				end
				else begin
					RD_FIFO_ONE <= 1'b0;
					fifo_sel[1]<=1'b1;
					operate_state <= 5'd4;//进入状态4
				end
			end
			5'd2:begin
				D422_c1_fe <= RFE_ONE_;//不过这里没有使用到这一位标志
				operate_state <= 5'd3;//进入状态3
			end
			5'd3:begin
				//RAM_CE1_ <= 1'b1;//拉高ram控制信号
				//RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd0;//进入状态0
				RD_FIFO_ONE <= 1'b1;//给出读fifo信号，该信号高有效
			end
			//==================================================================================//
			5'd4:begin//这里应该首先加入判断，防止只有一路422工作的bug
				if(RFE_TWO_ == 1)begin                    //如果fifo没有被读空
					operate_state <= 5'd5;//进入状态5
					RD_FIFO_TWO <= 1'b0;  
				end
				else begin//如果fifo被读空了
					RD_FIFO_TWO <= 1'b0;
					fifo_sel[2]<=1'b1;
					operate_state <= 5'd8;//进入状态8
				end
			end
			5'd5:begin
			if(RFE_TWO_ == 1)begin                    //如果fifo没有被读空
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//计数器+1//eulerhit
					//RAM_CE1_ <= 1'b0;                     //加入写ram控制信号3个
					//RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd6;  
					//*****************************
					fifo_sel[2]<=1'b0;
				end
			else begin//如果fifo被读空了
					RD_FIFO_TWO <= 1'b0;
					fifo_sel[2]<=1'b1;
					operate_state <= 5'd8;//进入状态8
				end
				
			end
			5'd6:begin
				D422_c2_fe <= RFE_TWO_;
				operate_state <= 5'd7;//进入状态7
			end
			5'd7:begin
				//RAM_CE1_ <= 1'b1;                    //拉高ram控制信号
				//RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd4;//进入状态4
				RD_FIFO_TWO <= 1'b1;//给出读fifo信号
			end
			//==================================================================================//
			5'd8:begin
				if(RFE_THREE_ == 1)begin                    //如果fifo没有被读空
					operate_state <= 5'd9;//进入状态9
					RD_FIFO_THREE <= 1'b0;                  //收回读fifo信号
				end
				else begin//如果fifo被读空了
					RD_FIFO_THREE <= 1'b0;
					fifo_sel[3]<=1'b1;
					operate_state <= 5'd12;//进入状态12
				end
			end
			5'd9:begin
			if(RFE_THREE_ == 1)	begin
				RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+计数器
				RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//计数器+1//eulerhit
				//RAM_CE1_ <= 1'b0;                     //加入写ram控制信号3个
				//RAM_CE2 <= 1'b1;
				RAM_WE_ <= 1'b0;
				operate_state <= 5'd10;//进入状态10              //这里fifo数据输出端直接连接到ram数据总线上
				//*****************************
				fifo_sel[3]<=1'b0;
				end
			else begin
				RD_FIFO_THREE <= 1'b0;
				operate_state <= 5'd12;//进入状态12
				fifo_sel[3]<=1'b1;
				end
			end
			5'd10:begin				
				D422_c3_fe <= RFE_THREE_;
				operate_state <= 5'd11;//进入状态11
			end
			5'd11:begin
				//RAM_CE1_ <= 1'b1;                    //拉高ram控制信号
				//RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd8;//进入状态8
				RD_FIFO_THREE <= 1'b1;//给出读fifo信号
			end
			//==================================================================================//
			5'd12:begin
				if(RFE_FORE_ == 1)begin                    //如果fifo没有被读空
					operate_state <= 5'd13;//进入状态13 
					RD_FIFO_FORE <= 1'b0;                  //收回读fifo信号
				end
				else begin//如果fifo被读空了
					RD_FIFO_FORE <= 1'b0;
					fifo_sel[4]<=1'b1;
					operate_state <= 5'd16;//进入状态16
				end
			end
			5'd13:begin
				if(RFE_FORE_ == 1)begin 
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//计数器+1//eulerhit
					//RAM_CE1_ <= 1'b0;                     //加入写ram控制信号3个
					//RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd14;//进入状态14         
					//*****************************
					fifo_sel[4]<=1'b0;
				end
				else begin
					RD_FIFO_FORE <= 1'b0;
					fifo_sel[4]<=1'b1;
					operate_state <= 5'd16;
				end
			end
			5'd14:begin
				D422_c4_fe <= RFE_FORE_;
				operate_state <= 5'd15;//进入状态15
			end
			5'd15:begin
				//RAM_CE1_ <= 1'b1;                    //拉高ram控制信号
				//RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				operate_state <= 5'd12;//进入状态12 
				RD_FIFO_FORE <= 1'b1;//给出读fifo信号
			end
			//==================================================================================//
			5'd16:begin
				if(RFE_232_ == 1)begin                    //如果fifo没有被读空
					operate_state <= 5'd17;//进入状态17
					RD_FIFO_232 <= 1'b0;                  //收回读fifo信号
				end
				else begin//如果fifo被读空了
					fifo_sel[0]<=1'b1;
					data_to_ram_en <= 1'b0;//表示模块向RAM写数据完毕
					operate_state <= 5'd20;//进入状态16
				end
			end
			5'd17:begin
				if(RFE_232_ == 1)begin  
					RAM_ADDR <= RAM_WRITE_ADDR_POINTER;//放入地址=首地址+计数器
					RAM_WRITE_ADDR_POINTER <= RAM_WRITE_ADDR_POINTER + 20'b01;//计数器+1//eulerhit
					//RAM_CE1_ <= 1'b0;                     //加入写ram控制信号3个
					//RAM_CE2 <= 1'b1;
					RAM_WE_ <= 1'b0;
					operate_state <= 5'd18;//进入状态18 
					//*****************************
					fifo_sel[0]<=1'b0;
					end
				else begin
					data_to_ram_en <= 1'b0;
					fifo_sel[0]<=1'b1;
					operate_state <= 5'd20;
					end
			end
			5'd18:begin			
			    D232_fe <= RFE_232_;
				operate_state <= 5'd19;//进入状态19
			end
			5'd19:begin
				//RAM_CE1_ <= 1'b1;                    //拉高ram控制信号
				//RAM_CE2 <= 1'b0;
				RAM_WE_ <= 1'b1;
				RD_FIFO_232 <= 1'b1;//给出读fifo信号
				operate_state <= 5'd16;//进入状态16
			end
			default:begin
				data_to_ram_en <= 1'b0;//表示模块向RAM写数据完毕
				busy_flag <= 1'b0;
				RAM_WE_ <= 1'b1;
				RD_FIFO_ONE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_TWO <= 1'b0;                  //收回读fifo信号
				RD_FIFO_THREE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_FORE <= 1'b0;                  //收回读fifo信号
				RD_FIFO_232 <= 1'b0;                  //收回读fifo信号
			end
			endcase
		end
		endcase
	end//2
	
end//1
//====================================================================================================//
always @ (*)
begin
	if(  ((half_full_state == 0) && (busy_flag == 0))	||	((timer_start_flag == 1) && (busy_flag == 0))   ) begin
		next_state = 2'd1;//如果任意一路422半满并且busy==0，或者定时器计数到5ms并且busy==0，则触发下一状态==1
	end
	else 
	begin 
		if(busy_flag == 0) begin
			next_state = 2'd0;
		end
		else begin
			next_state = current_state;
		end
	end
end
//====================================================================================================//
//状态转换，将下一状态赋值给当前状态
always @(posedge CLK)
begin
    current_state <= next_state;
end
//====================================================================================================//
//定时器计数器
reg timer_start_flag;//定时器有效标志，当这一位有效，表示定时器计数到5ms，开始查询，高有效，低无效
parameter time_delay = 20'b10_0100_1111_1101_1011;//20'd151515 time = 151515*33ns = 4.999995ms
reg [19:0] timer;
always @ (posedge CLK or negedge reset_)
if (!reset_)begin
	timer <= 20'b0;
	timer_start_flag <= 1'b0;
end
else begin
	if(timer <= time_delay - 20'd1)begin
		timer <= timer + 20'b1;
	end
	else if(timer <= time_delay + 20'd1) begin
		if(busy_flag == 1'b1)begin//如果busy==1，表示正在工作，则如果计数器达到计数时间，则需要延迟数个周期
			timer <= timer;
			timer_start_flag <= 1'b1;
		end
		else begin
			timer <= timer + 20'b1;
			timer_start_flag <= 1'b1;
		end		
	end 
	else begin
		timer <= 20'd0;
		timer_start_flag <= 1'b0;
	end
end
//==================================================================================//
endmodule