📄 mux6.rpt
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07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zzr\eda\shizhong\mux6.rpt
mux6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 cp1
Device-Specific Information: d:\zzr\eda\shizhong\mux6.rpt
mux6
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 reset
Device-Specific Information: d:\zzr\eda\shizhong\mux6.rpt
mux6
** EQUATIONS **
cnthh0 : INPUT;
cnthh1 : INPUT;
cnthh2 : INPUT;
cnthh3 : INPUT;
cnthl0 : INPUT;
cnthl1 : INPUT;
cnthl2 : INPUT;
cnthl3 : INPUT;
cntmh0 : INPUT;
cntmh1 : INPUT;
cntmh2 : INPUT;
cntmh3 : INPUT;
cntml0 : INPUT;
cntml1 : INPUT;
cntml2 : INPUT;
cntml3 : INPUT;
cntsh0 : INPUT;
cntsh1 : INPUT;
cntsh2 : INPUT;
cntsh3 : INPUT;
cntsl0 : INPUT;
cntsl1 : INPUT;
cntsl2 : INPUT;
cntsl3 : INPUT;
cp1 : INPUT;
reset : INPUT;
-- Node name is 'cntout0'
-- Equation name is 'cntout0', type is output
cntout0 = _LC2_A2;
-- Node name is 'cntout1'
-- Equation name is 'cntout1', type is output
cntout1 = _LC7_A6;
-- Node name is 'cntout2'
-- Equation name is 'cntout2', type is output
cntout2 = _LC1_A2;
-- Node name is 'cntout3'
-- Equation name is 'cntout3', type is output
cntout3 = _LC1_A7;
-- Node name is ':36' = 'sel0'
-- Equation name is 'sel0', location is LC1_A5, type is buried.
sel0 = DFFE( _EQ001, GLOBAL( cp1), GLOBAL( reset), VCC, VCC);
_EQ001 = !sel0 & !sel1
# !sel0 & !sel2;
-- Node name is ':35' = 'sel1'
-- Equation name is 'sel1', location is LC7_A5, type is buried.
sel1 = DFFE( _EQ002, GLOBAL( cp1), GLOBAL( reset), VCC, VCC);
_EQ002 = !sel0 & sel1 & !sel2
# sel0 & !sel1 & !sel2;
-- Node name is ':34' = 'sel2'
-- Equation name is 'sel2', location is LC3_A5, type is buried.
sel2 = DFFE( _EQ003, GLOBAL( cp1), GLOBAL( reset), VCC, VCC);
_EQ003 = sel0 & sel1 & !sel2
# !sel0 & !sel1 & sel2;
-- Node name is 'set0'
-- Equation name is 'set0', type is output
set0 = sel0;
-- Node name is 'set1'
-- Equation name is 'set1', type is output
set1 = sel1;
-- Node name is 'set2'
-- Equation name is 'set2', type is output
set2 = sel2;
-- Node name is ':335'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = LCELL( _EQ004);
_EQ004 = cnthl3 & !sel0 & !sel1 & sel2;
-- Node name is ':336'
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = LCELL( _EQ005);
_EQ005 = cnthh3 & sel0 & !sel1 & sel2;
-- Node name is ':341'
-- Equation name is '_LC8_A5', type is buried
!_LC8_A5 = _LC8_A5~NOT;
_LC8_A5~NOT = LCELL( _EQ006);
_EQ006 = !sel1
# !sel0
# sel2;
-- Node name is ':344'
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = LCELL( _EQ007);
_EQ007 = cntmh3 & _LC8_A5
# _LC3_A7 & !_LC8_A5
# _LC4_A7 & !_LC8_A5;
-- Node name is ':351'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = LCELL( _EQ008);
_EQ008 = !sel0 & sel1 & !sel2;
-- Node name is ':354'
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = LCELL( _EQ009);
_EQ009 = !_LC2_A7 & _LC5_A7
# cntml3 & _LC2_A7;
-- Node name is ':361'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ010);
_EQ010 = sel0 & !sel1 & !sel2;
-- Node name is ':364'
-- Equation name is '_LC7_A7', type is buried
_LC7_A7 = LCELL( _EQ011);
_EQ011 = !_LC2_A6 & _LC6_A7
# cntsh3 & _LC2_A6;
-- Node name is ':371'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ012);
_EQ012 = !sel0 & !sel1 & !sel2;
-- Node name is ':374'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ013);
_EQ013 = !_LC1_A6 & _LC7_A7
# cntsl3 & _LC1_A6;
-- Node name is ':384'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ014);
_EQ014 = cnthl2 & !sel0 & !sel1 & sel2;
-- Node name is ':385'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ015);
_EQ015 = cnthh2 & sel0 & !sel1 & sel2;
-- Node name is ':386'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = LCELL( _EQ016);
_EQ016 = cntmh2 & _LC8_A5
# _LC5_A2 & !_LC8_A5
# _LC4_A5 & !_LC8_A5;
-- Node name is ':389'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ017);
_EQ017 = !_LC2_A7 & _LC6_A2
# cntml2 & _LC2_A7;
-- Node name is ':392'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ018);
_EQ018 = !_LC2_A6 & _LC7_A2
# cntsh2 & _LC2_A6;
-- Node name is ':395'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ019);
_EQ019 = !_LC1_A6 & _LC8_A2
# cntsl2 & _LC1_A6;
-- Node name is ':405'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ020);
_EQ020 = cnthl1 & !sel0 & !sel1 & sel2;
-- Node name is ':406'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = LCELL( _EQ021);
_EQ021 = cnthh1 & sel0 & !sel1 & sel2;
-- Node name is ':407'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ022);
_EQ022 = cntmh1 & _LC8_A5
# _LC3_A6 & !_LC8_A5
# _LC4_A6 & !_LC8_A5;
-- Node name is ':410'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ023);
_EQ023 = !_LC2_A7 & _LC5_A6
# cntml1 & _LC2_A7;
-- Node name is ':413'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ024);
_EQ024 = !_LC2_A6 & _LC6_A6
# cntsh1 & _LC2_A6;
-- Node name is ':416'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ025);
_EQ025 = !_LC1_A6 & _LC8_A6
# cntsl1 & _LC1_A6;
-- Node name is ':426'
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ026);
_EQ026 = cnthl0 & !sel0 & !sel1 & sel2;
-- Node name is ':427'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ027);
_EQ027 = cnthh0 & sel0 & !sel1 & sel2;
-- Node name is ':428'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = LCELL( _EQ028);
_EQ028 = cntmh0 & _LC8_A5
# _LC2_A5 & !_LC8_A5
# _LC6_A5 & !_LC8_A5;
-- Node name is ':431'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ029);
_EQ029 = !_LC2_A7 & _LC5_A5
# cntml0 & _LC2_A7;
-- Node name is ':434'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ030);
_EQ030 = !_LC2_A6 & _LC3_A2
# cntsh0 & _LC2_A6;
-- Node name is ':437'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ031);
_EQ031 = !_LC1_A6 & _LC4_A2
# cntsl0 & _LC1_A6;
Project Information d:\zzr\eda\shizhong\mux6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,381K
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