decoder48.vhd

数字钟的VHDL源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder48 is
port(d:in std_logic_vector(3 downto 0);
     seg:out std_logic_vector(7 downto 0));
end decoder48;
architecture str of decoder48 is
begin
seg<="00111111" when d="0000" else
     "00000110" when d="0001" else
	 "01011011" when d="0010" else
     "01001111" when d="0011" else
     "01100110" when d="0100" else
     "01101101" when d="0101" else
     "01111101" when d="0110" else
     "00000111" when d="0111" else
     "01111111" when d="1000" else
     "01100111" when d="1001" else
     "00000000";
end str;